JP2006500725A5 - - Google Patents

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Publication number
JP2006500725A5
JP2006500725A5 JP2004539810A JP2004539810A JP2006500725A5 JP 2006500725 A5 JP2006500725 A5 JP 2006500725A5 JP 2004539810 A JP2004539810 A JP 2004539810A JP 2004539810 A JP2004539810 A JP 2004539810A JP 2006500725 A5 JP2006500725 A5 JP 2006500725A5
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JP
Japan
Prior art keywords
transistor
reference voltage
memory cell
current electrode
control electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004539810A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006500725A (ja
JP4322809B2 (ja
Filing date
Publication date
Priority claimed from US10/255,303 external-priority patent/US6538940B1/en
Application filed filed Critical
Publication of JP2006500725A publication Critical patent/JP2006500725A/ja
Publication of JP2006500725A5 publication Critical patent/JP2006500725A5/ja
Application granted granted Critical
Publication of JP4322809B2 publication Critical patent/JP4322809B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2004539810A 2002-09-26 2003-07-22 Mramの弱ビットを特定する方法及び回路 Expired - Fee Related JP4322809B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/255,303 US6538940B1 (en) 2002-09-26 2002-09-26 Method and circuitry for identifying weak bits in an MRAM
PCT/US2003/022851 WO2004029987A1 (en) 2002-09-26 2003-07-22 Method and circuitry for identifying weak bits in an mram

Publications (3)

Publication Number Publication Date
JP2006500725A JP2006500725A (ja) 2006-01-05
JP2006500725A5 true JP2006500725A5 (enExample) 2006-07-20
JP4322809B2 JP4322809B2 (ja) 2009-09-02

Family

ID=22967712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004539810A Expired - Fee Related JP4322809B2 (ja) 2002-09-26 2003-07-22 Mramの弱ビットを特定する方法及び回路

Country Status (9)

Country Link
US (1) US6538940B1 (enExample)
EP (1) EP1547094B1 (enExample)
JP (1) JP4322809B2 (enExample)
KR (1) KR100985400B1 (enExample)
CN (1) CN100416706C (enExample)
AU (1) AU2003252100A1 (enExample)
DE (1) DE60311117T2 (enExample)
TW (1) TWI299870B (enExample)
WO (1) WO2004029987A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6600690B1 (en) * 2002-06-28 2003-07-29 Motorola, Inc. Sense amplifier for a memory having at least two distinct resistance states
JP4266297B2 (ja) * 2002-09-05 2009-05-20 株式会社ルネサステクノロジ 不揮発性記憶装置
US6707710B1 (en) * 2002-12-12 2004-03-16 Hewlett-Packard Development Company, L.P. Magnetic memory device with larger reference cell
US6999887B2 (en) * 2003-08-06 2006-02-14 Infineon Technologies Ag Memory cell signal window testing apparatus
KR100988087B1 (ko) * 2003-11-24 2010-10-18 삼성전자주식회사 Mram 특성 분석 장치 및 그 분석 방법
US7038959B2 (en) * 2004-09-17 2006-05-02 Freescale Semiconductor, Inc. MRAM sense amplifier having a precharge circuit and method for sensing
US7110313B2 (en) * 2005-01-04 2006-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-time electrical fuse programming circuit
EP1787535B1 (en) * 2005-11-16 2013-07-03 Cho, Eun Hyo Pants having body-shaping function
US7313043B2 (en) * 2005-11-29 2007-12-25 Altis Semiconductor Snc Magnetic Memory Array
CN101842843B (zh) * 2007-11-01 2014-06-11 飞思卡尔半导体公司 Mram测试
US8780657B2 (en) 2012-03-01 2014-07-15 Apple Inc. Memory with bit line current injection
US9165629B2 (en) * 2013-03-12 2015-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for MRAM sense reference trimming
KR102150469B1 (ko) * 2014-04-04 2020-09-02 에스케이하이닉스 주식회사 저항성 메모리 장치
US10290327B2 (en) * 2017-10-13 2019-05-14 Nantero, Inc. Devices and methods for accessing resistive change elements in resistive change element arrays
US10224088B1 (en) * 2018-02-12 2019-03-05 Nxp Usa, Inc. Memory with a global reference circuit
US10839879B2 (en) * 2018-09-27 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Read techniques for a magnetic tunnel junction (MTJ) memory device with a current mirror
CN112349321B (zh) * 2019-08-06 2024-03-12 上海磁宇信息科技有限公司 一种使用公共参考电压的磁性随机存储器芯片架构
CN116343884A (zh) * 2021-12-23 2023-06-27 浙江驰拓科技有限公司 Mram芯片的数据读取电路及筛选失效单元的方法
US12027224B2 (en) 2022-03-16 2024-07-02 International Business Machines Corporation Authenticity and yield by reading defective cells

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468759A (en) 1982-05-03 1984-08-28 Intel Corporation Testing method and apparatus for dram
US5142495A (en) * 1989-03-10 1992-08-25 Intel Corporation Variable load for margin mode
US5321842A (en) * 1990-01-13 1994-06-14 At&T Bell Laboratories Three-state driver with feedback-controlled switching
US6105152A (en) 1993-04-13 2000-08-15 Micron Technology, Inc. Devices and methods for testing cell margin of memory devices
US5537358A (en) 1994-12-06 1996-07-16 National Semiconductor Corporation Flash memory having adaptive sensing and method
US5731733A (en) * 1995-09-29 1998-03-24 Intel Corporation Static, low current sensing circuit for sensing the state of a fuse device
FR2760888B1 (fr) * 1997-03-11 1999-05-07 Sgs Thomson Microelectronics Circuit de lecture pour memoire adapte a la mesure des courants de fuite
US6128239A (en) * 1999-10-29 2000-10-03 Hewlett-Packard MRAM device including analog sense amplifiers
US6317376B1 (en) * 2000-06-20 2001-11-13 Hewlett-Packard Company Reference signal generation for magnetic random access memory devices
JP3596808B2 (ja) * 2000-08-10 2004-12-02 沖電気工業株式会社 不揮発性半導体記憶装置
US6456524B1 (en) * 2001-10-31 2002-09-24 Hewlett-Packard Company Hybrid resistive cross point memory cell arrays and methods of making the same

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