KR100985400B1 - 자기저항 랜덤 액세스 메모리 내의 위크 비트들을 식별하기위한 방법 및 회로 - Google Patents

자기저항 랜덤 액세스 메모리 내의 위크 비트들을 식별하기위한 방법 및 회로 Download PDF

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KR100985400B1
KR100985400B1 KR1020057005218A KR20057005218A KR100985400B1 KR 100985400 B1 KR100985400 B1 KR 100985400B1 KR 1020057005218 A KR1020057005218 A KR 1020057005218A KR 20057005218 A KR20057005218 A KR 20057005218A KR 100985400 B1 KR100985400 B1 KR 100985400B1
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transistor
reference voltage
memory cell
memory
current electrode
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Korean (ko)
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KR20050057585A (ko
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조세프 제이. 나하스
토마스 더블유. 안드레
브래들리 제이. 가르니
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프리스케일 세미컨덕터, 인크.
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
KR1020057005218A 2002-09-26 2003-07-22 자기저항 랜덤 액세스 메모리 내의 위크 비트들을 식별하기위한 방법 및 회로 Expired - Fee Related KR100985400B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/255,303 2002-09-26
US10/255,303 US6538940B1 (en) 2002-09-26 2002-09-26 Method and circuitry for identifying weak bits in an MRAM

Publications (2)

Publication Number Publication Date
KR20050057585A KR20050057585A (ko) 2005-06-16
KR100985400B1 true KR100985400B1 (ko) 2010-10-06

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057005218A Expired - Fee Related KR100985400B1 (ko) 2002-09-26 2003-07-22 자기저항 랜덤 액세스 메모리 내의 위크 비트들을 식별하기위한 방법 및 회로

Country Status (9)

Country Link
US (1) US6538940B1 (enExample)
EP (1) EP1547094B1 (enExample)
JP (1) JP4322809B2 (enExample)
KR (1) KR100985400B1 (enExample)
CN (1) CN100416706C (enExample)
AU (1) AU2003252100A1 (enExample)
DE (1) DE60311117T2 (enExample)
TW (1) TWI299870B (enExample)
WO (1) WO2004029987A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6600690B1 (en) * 2002-06-28 2003-07-29 Motorola, Inc. Sense amplifier for a memory having at least two distinct resistance states
JP4266297B2 (ja) * 2002-09-05 2009-05-20 株式会社ルネサステクノロジ 不揮発性記憶装置
US6707710B1 (en) * 2002-12-12 2004-03-16 Hewlett-Packard Development Company, L.P. Magnetic memory device with larger reference cell
US6999887B2 (en) * 2003-08-06 2006-02-14 Infineon Technologies Ag Memory cell signal window testing apparatus
KR100988087B1 (ko) * 2003-11-24 2010-10-18 삼성전자주식회사 Ｍｒａｍ 특성 분석 장치 및 그 분석 방법
US7038959B2 (en) * 2004-09-17 2006-05-02 Freescale Semiconductor, Inc. MRAM sense amplifier having a precharge circuit and method for sensing
US7110313B2 (en) * 2005-01-04 2006-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-time electrical fuse programming circuit
EP1787535B1 (en) * 2005-11-16 2013-07-03 Cho, Eun Hyo Pants having body-shaping function
US7313043B2 (en) * 2005-11-29 2007-12-25 Altis Semiconductor Snc Magnetic Memory Array
CN101842843B (zh) * 2007-11-01 2014-06-11 飞思卡尔半导体公司 Mram测试
US8780657B2 (en) 2012-03-01 2014-07-15 Apple Inc. Memory with bit line current injection
US9165629B2 (en) * 2013-03-12 2015-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for MRAM sense reference trimming
KR102150469B1 (ko) * 2014-04-04 2020-09-02 에스케이하이닉스 주식회사 저항성 메모리 장치
US10290327B2 (en) * 2017-10-13 2019-05-14 Nantero, Inc. Devices and methods for accessing resistive change elements in resistive change element arrays
US10224088B1 (en) * 2018-02-12 2019-03-05 Nxp Usa, Inc. Memory with a global reference circuit
US10839879B2 (en) * 2018-09-27 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Read techniques for a magnetic tunnel junction (MTJ) memory device with a current mirror
CN112349321B (zh) * 2019-08-06 2024-03-12 上海磁宇信息科技有限公司 一种使用公共参考电压的磁性随机存储器芯片架构
CN116343884A (zh) * 2021-12-23 2023-06-27 浙江驰拓科技有限公司 Mram芯片的数据读取电路及筛选失效单元的方法
US12027224B2 (en) 2022-03-16 2024-07-02 International Business Machines Corporation Authenticity and yield by reading defective cells

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020021605A1 (en) 2000-08-10 2002-02-21 Teruhiro Harada Nonvolatile semiconductor memory with testing circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468759A (en) 1982-05-03 1984-08-28 Intel Corporation Testing method and apparatus for dram
US5142495A (en) * 1989-03-10 1992-08-25 Intel Corporation Variable load for margin mode
US5321842A (en) * 1990-01-13 1994-06-14 At&T Bell Laboratories Three-state driver with feedback-controlled switching
US6105152A (en) 1993-04-13 2000-08-15 Micron Technology, Inc. Devices and methods for testing cell margin of memory devices
US5537358A (en) 1994-12-06 1996-07-16 National Semiconductor Corporation Flash memory having adaptive sensing and method
US5731733A (en) * 1995-09-29 1998-03-24 Intel Corporation Static, low current sensing circuit for sensing the state of a fuse device
FR2760888B1 (fr) * 1997-03-11 1999-05-07 Sgs Thomson Microelectronics Circuit de lecture pour memoire adapte a la mesure des courants de fuite
US6128239A (en) * 1999-10-29 2000-10-03 Hewlett-Packard MRAM device including analog sense amplifiers
US6317376B1 (en) * 2000-06-20 2001-11-13 Hewlett-Packard Company Reference signal generation for magnetic random access memory devices
US6456524B1 (en) * 2001-10-31 2002-09-24 Hewlett-Packard Company Hybrid resistive cross point memory cell arrays and methods of making the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020021605A1 (en) 2000-08-10 2002-02-21 Teruhiro Harada Nonvolatile semiconductor memory with testing circuit

Also Published As

Publication number Publication date
JP2006500725A (ja) 2006-01-05
EP1547094A1 (en) 2005-06-29
EP1547094B1 (en) 2007-01-10
JP4322809B2 (ja) 2009-09-02
KR20050057585A (ko) 2005-06-16
WO2004029987A1 (en) 2004-04-08
DE60311117D1 (de) 2007-02-22
AU2003252100A1 (en) 2004-04-19
US6538940B1 (en) 2003-03-25
TWI299870B (en) 2008-08-11
CN100416706C (zh) 2008-09-03
DE60311117T2 (de) 2007-08-16
TW200423140A (en) 2004-11-01
CN1685445A (zh) 2005-10-19

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