DE60311117D1 - Verfahren und schaltkreise zum identifizieren schwacher bit in einem mram - Google Patents
Verfahren und schaltkreise zum identifizieren schwacher bit in einem mramInfo
- Publication number
- DE60311117D1 DE60311117D1 DE60311117T DE60311117T DE60311117D1 DE 60311117 D1 DE60311117 D1 DE 60311117D1 DE 60311117 T DE60311117 T DE 60311117T DE 60311117 T DE60311117 T DE 60311117T DE 60311117 D1 DE60311117 D1 DE 60311117D1
- Authority
- DE
- Germany
- Prior art keywords
- mram
- circuits
- weak bit
- identifying weak
- identifying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US255303 | 2002-09-26 | ||
| US10/255,303 US6538940B1 (en) | 2002-09-26 | 2002-09-26 | Method and circuitry for identifying weak bits in an MRAM |
| PCT/US2003/022851 WO2004029987A1 (en) | 2002-09-26 | 2003-07-22 | Method and circuitry for identifying weak bits in an mram |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60311117D1 true DE60311117D1 (de) | 2007-02-22 |
| DE60311117T2 DE60311117T2 (de) | 2007-08-16 |
Family
ID=22967712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60311117T Expired - Fee Related DE60311117T2 (de) | 2002-09-26 | 2003-07-22 | Verfahren und schaltkreise zum identifizieren schwacher bit in einem mram |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US6538940B1 (de) |
| EP (1) | EP1547094B1 (de) |
| JP (1) | JP4322809B2 (de) |
| KR (1) | KR100985400B1 (de) |
| CN (1) | CN100416706C (de) |
| AU (1) | AU2003252100A1 (de) |
| DE (1) | DE60311117T2 (de) |
| TW (1) | TWI299870B (de) |
| WO (1) | WO2004029987A1 (de) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6600690B1 (en) * | 2002-06-28 | 2003-07-29 | Motorola, Inc. | Sense amplifier for a memory having at least two distinct resistance states |
| JP4266297B2 (ja) * | 2002-09-05 | 2009-05-20 | 株式会社ルネサステクノロジ | 不揮発性記憶装置 |
| US6707710B1 (en) * | 2002-12-12 | 2004-03-16 | Hewlett-Packard Development Company, L.P. | Magnetic memory device with larger reference cell |
| US6999887B2 (en) * | 2003-08-06 | 2006-02-14 | Infineon Technologies Ag | Memory cell signal window testing apparatus |
| KR100988087B1 (ko) * | 2003-11-24 | 2010-10-18 | 삼성전자주식회사 | Ｍｒａｍ 특성 분석 장치 및 그 분석 방법 |
| US7038959B2 (en) * | 2004-09-17 | 2006-05-02 | Freescale Semiconductor, Inc. | MRAM sense amplifier having a precharge circuit and method for sensing |
| US7110313B2 (en) * | 2005-01-04 | 2006-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-time electrical fuse programming circuit |
| US7950069B2 (en) * | 2005-11-16 | 2011-05-31 | Eun Hyo Cho | Pants having body-shaping function |
| US7313043B2 (en) * | 2005-11-29 | 2007-12-25 | Altis Semiconductor Snc | Magnetic Memory Array |
| CN101842843B (zh) * | 2007-11-01 | 2014-06-11 | 飞思卡尔半导体公司 | Mram测试 |
| US8780657B2 (en) | 2012-03-01 | 2014-07-15 | Apple Inc. | Memory with bit line current injection |
| US9165629B2 (en) * | 2013-03-12 | 2015-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for MRAM sense reference trimming |
| KR102150469B1 (ko) * | 2014-04-04 | 2020-09-02 | 에스케이하이닉스 주식회사 | 저항성 메모리 장치 |
| US10290327B2 (en) * | 2017-10-13 | 2019-05-14 | Nantero, Inc. | Devices and methods for accessing resistive change elements in resistive change element arrays |
| US10224088B1 (en) * | 2018-02-12 | 2019-03-05 | Nxp Usa, Inc. | Memory with a global reference circuit |
| US10839879B2 (en) * | 2018-09-27 | 2020-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Read techniques for a magnetic tunnel junction (MTJ) memory device with a current mirror |
| CN112349321B (zh) * | 2019-08-06 | 2024-03-12 | 上海磁宇信息科技有限公司 | 一种使用公共参考电压的磁性随机存储器芯片架构 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4468759A (en) | 1982-05-03 | 1984-08-28 | Intel Corporation | Testing method and apparatus for dram |
| US5142495A (en) * | 1989-03-10 | 1992-08-25 | Intel Corporation | Variable load for margin mode |
| US5321842A (en) * | 1990-01-13 | 1994-06-14 | At&T Bell Laboratories | Three-state driver with feedback-controlled switching |
| US6105152A (en) | 1993-04-13 | 2000-08-15 | Micron Technology, Inc. | Devices and methods for testing cell margin of memory devices |
| US5537358A (en) | 1994-12-06 | 1996-07-16 | National Semiconductor Corporation | Flash memory having adaptive sensing and method |
| US5731733A (en) * | 1995-09-29 | 1998-03-24 | Intel Corporation | Static, low current sensing circuit for sensing the state of a fuse device |
| FR2760888B1 (fr) * | 1997-03-11 | 1999-05-07 | Sgs Thomson Microelectronics | Circuit de lecture pour memoire adapte a la mesure des courants de fuite |
| US6128239A (en) * | 1999-10-29 | 2000-10-03 | Hewlett-Packard | MRAM device including analog sense amplifiers |
| US6317376B1 (en) * | 2000-06-20 | 2001-11-13 | Hewlett-Packard Company | Reference signal generation for magnetic random access memory devices |
| JP3596808B2 (ja) | 2000-08-10 | 2004-12-02 | 沖電気工業株式会社 | 不揮発性半導体記憶装置 |
| US6456524B1 (en) * | 2001-10-31 | 2002-09-24 | Hewlett-Packard Company | Hybrid resistive cross point memory cell arrays and methods of making the same |
-
2002
- 2002-09-26 US US10/255,303 patent/US6538940B1/en not_active Expired - Fee Related
-
2003
- 2003-07-22 JP JP2004539810A patent/JP4322809B2/ja not_active Expired - Fee Related
- 2003-07-22 CN CNB038229684A patent/CN100416706C/zh not_active Expired - Fee Related
- 2003-07-22 KR KR1020057005218A patent/KR100985400B1/ko not_active IP Right Cessation
- 2003-07-22 EP EP03798674A patent/EP1547094B1/de not_active Expired - Lifetime
- 2003-07-22 WO PCT/US2003/022851 patent/WO2004029987A1/en active IP Right Grant
- 2003-07-22 DE DE60311117T patent/DE60311117T2/de not_active Expired - Fee Related
- 2003-07-22 AU AU2003252100A patent/AU2003252100A1/en not_active Abandoned
- 2003-09-10 TW TW092125077A patent/TWI299870B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| DE60311117T2 (de) | 2007-08-16 |
| KR20050057585A (ko) | 2005-06-16 |
| AU2003252100A1 (en) | 2004-04-19 |
| TW200423140A (en) | 2004-11-01 |
| TWI299870B (en) | 2008-08-11 |
| JP4322809B2 (ja) | 2009-09-02 |
| WO2004029987A1 (en) | 2004-04-08 |
| EP1547094A1 (de) | 2005-06-29 |
| CN100416706C (zh) | 2008-09-03 |
| KR100985400B1 (ko) | 2010-10-06 |
| CN1685445A (zh) | 2005-10-19 |
| EP1547094B1 (de) | 2007-01-10 |
| JP2006500725A (ja) | 2006-01-05 |
| US6538940B1 (en) | 2003-03-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |