JP4047315B2 - 記憶素子の値を求めるためのシステム及び方法 - Google Patents
記憶素子の値を求めるためのシステム及び方法 Download PDFInfo
- Publication number
- JP4047315B2 JP4047315B2 JP2004263172A JP2004263172A JP4047315B2 JP 4047315 B2 JP4047315 B2 JP 4047315B2 JP 2004263172 A JP2004263172 A JP 2004263172A JP 2004263172 A JP2004263172 A JP 2004263172A JP 4047315 B2 JP4047315 B2 JP 4047315B2
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- Prior art keywords
- mem
- storage element
- voltage
- current
- column
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
102 中央処理装置(CPU)
104 メモリ
212 記憶素子(メモリ素子)
224 利得段
226 コントローラ
Claims (5)
- 複数の記憶素子(212)のうちのある記憶素子の値を求める方法であって、
2つの入力と1つの出力を有し、前記出力が前記入力のうちの一方の入力に接続された利得段を提供するステップであって、前記利得段は、2つの入力における電圧が等しくなるように動作することからなる、ステップと、
前記利得段の他方の入力に第1の電圧V Y を印加するステップと、
所望の記憶素子RMEMを含んでいる対象とする列を選択するステップ(500)と、
前記列中の所望されていない記憶素子R LEAK の一方の端子が前記利得段の前記一方の入力に接続された状態で、前記列中の所望されていない記憶素子R LEAK から前記所望の記憶素子R MEM を分離するための電圧を、前記所望されていない記憶素子R LEAK の他方の端子に印加するステップ(502)と、
前記所望の記憶素子R MEM の一方の端子を前記利得段の前記一方の入力に接続した状態で、前記所望の記憶素子RMEMをディスエーブルにするための電圧を、該所望の記憶素子R MEM の他方の端子に印加するステップ(504)と、
前記対象とする列に供給される第1の電流ISENSEを測定するステップ(506)と、
前記利得段の入力オフセット電圧を調整して、前記所望されていない記憶素子RLEAKに流れる電流を補償するステップ(508)と、
前記所望の記憶素子RMEM の前記他方の端子に該所望の記憶素子R MEM をイネーブルにするための電圧を印加するステップ(510)と、
前記対象とする列に供給される第2の電流ISENSEを測定するステップ(512)
を含む、方法。 - 対象とする列を選択する前記ステップ(500)が、それぞれの列に電圧を結合するステップを含む、請求項1に記載の方法。
- 所望の記憶素子RMEMをディスエーブルにする前記ステップ(504)において、前記所望の記憶素子R MEM をディスエーブルにするための電圧を、該所望の記憶素子R MEM の前記他方の端子に印加するのに代えて、前記所望の記憶素子RMEM の前記他方の端子を高インピーダンス状態に結合することからなる、請求項1に記載の方法。
- 前記第1の電流の測定値(506)が、所望されていない記憶素子RLEAKに流れる電流量に対応し、
前記第2の電流の測定値(512)が、前記所望の記憶素子RMEMのディジタル値に対応することからなる、請求項1に記載の方法。 - 所望の記憶素子RMEMをイネーブルにするための電圧を印加する前記ステップ(510)が、前記所望の記憶素子RMEM の前記他方の端子をアースに結合するステップである、請求項1に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/662,643 US6970387B2 (en) | 2003-09-15 | 2003-09-15 | System and method for determining the value of a memory element |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005093049A JP2005093049A (ja) | 2005-04-07 |
JP4047315B2 true JP4047315B2 (ja) | 2008-02-13 |
Family
ID=34274161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004263172A Expired - Fee Related JP4047315B2 (ja) | 2003-09-15 | 2004-09-10 | 記憶素子の値を求めるためのシステム及び方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6970387B2 (ja) |
JP (1) | JP4047315B2 (ja) |
DE (1) | DE102004023842A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8310858B2 (en) | 2009-09-01 | 2012-11-13 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device with no decrease in read margin and method of reading the same |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4199781B2 (ja) * | 2006-04-12 | 2008-12-17 | シャープ株式会社 | 不揮発性半導体記憶装置 |
KR20130030616A (ko) * | 2011-09-19 | 2013-03-27 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 |
WO2013084412A1 (ja) | 2011-12-07 | 2013-06-13 | パナソニック株式会社 | クロスポイント型不揮発性記憶装置とそのフォーミング方法 |
KR20130069029A (ko) * | 2011-12-16 | 2013-06-26 | 에스케이하이닉스 주식회사 | 저항성 메모리 장치 |
WO2013153786A1 (ja) | 2012-04-09 | 2013-10-17 | パナソニック株式会社 | 不揮発性記憶装置、およびそのフォーミング方法 |
WO2016137437A1 (en) * | 2015-02-24 | 2016-09-01 | Hewlett Packard Enterprise Development Lp | Determining a state of a memristor cell |
US9934848B2 (en) | 2016-06-07 | 2018-04-03 | Nantero, Inc. | Methods for determining the resistive states of resistive change elements |
US9941001B2 (en) * | 2016-06-07 | 2018-04-10 | Nantero, Inc. | Circuits for determining the resistive states of resistive change elements |
US10475510B2 (en) | 2017-12-21 | 2019-11-12 | Macronix International Co., Ltd. | Leakage compensation read method for memory device |
US11081157B2 (en) * | 2018-12-11 | 2021-08-03 | Micron Technology, Inc. | Leakage compensation for memory arrays |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10033486A1 (de) * | 2000-07-10 | 2002-01-24 | Infineon Technologies Ag | Integrierter Speicher mit Speicherzellen mit magnetoresistivem Speichereffekt |
JP3812805B2 (ja) * | 2001-01-16 | 2006-08-23 | 日本電気株式会社 | トンネル磁気抵抗素子を利用した半導体記憶装置 |
US6597600B2 (en) * | 2001-08-27 | 2003-07-22 | Micron Technology, Inc. | Offset compensated sensing for magnetic random access memory |
US6829188B2 (en) * | 2002-08-19 | 2004-12-07 | Micron Technology, Inc. | Dual loop sensing scheme for resistive memory elements |
US7027318B2 (en) * | 2003-05-30 | 2006-04-11 | Hewlett-Packard Development Company, L.P. | Method and system for adjusting offset voltage |
US6901005B2 (en) * | 2003-08-27 | 2005-05-31 | Hewlett-Packard Development Company, L.P. | Method and system reading magnetic memory |
-
2003
- 2003-09-15 US US10/662,643 patent/US6970387B2/en not_active Expired - Lifetime
-
2004
- 2004-05-13 DE DE102004023842A patent/DE102004023842A1/de not_active Ceased
- 2004-09-10 JP JP2004263172A patent/JP4047315B2/ja not_active Expired - Fee Related
-
2005
- 2005-08-25 US US11/212,936 patent/US7324370B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8310858B2 (en) | 2009-09-01 | 2012-11-13 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device with no decrease in read margin and method of reading the same |
Also Published As
Publication number | Publication date |
---|---|
US20060002193A1 (en) | 2006-01-05 |
JP2005093049A (ja) | 2005-04-07 |
US20050057974A1 (en) | 2005-03-17 |
US7324370B2 (en) | 2008-01-29 |
US6970387B2 (en) | 2005-11-29 |
DE102004023842A1 (de) | 2005-05-04 |
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