JP4031447B2 - オフセット調整可能な差動増幅器 - Google Patents
オフセット調整可能な差動増幅器 Download PDFInfo
- Publication number
- JP4031447B2 JP4031447B2 JP2004015416A JP2004015416A JP4031447B2 JP 4031447 B2 JP4031447 B2 JP 4031447B2 JP 2004015416 A JP2004015416 A JP 2004015416A JP 2004015416 A JP2004015416 A JP 2004015416A JP 4031447 B2 JP4031447 B2 JP 4031447B2
- Authority
- JP
- Japan
- Prior art keywords
- differential
- sub
- offset
- transistor
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/067—Single-ended amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
- H03F3/45766—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means
- H03F3/45771—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means using switching means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45212—Indexing scheme relating to differential amplifiers the differential amplifier being designed to have a reduced offset
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45342—Indexing scheme relating to differential amplifiers the AAC comprising control means on a back gate of the AAC
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45371—Indexing scheme relating to differential amplifiers the AAC comprising parallel coupled multiple transistors at their source and gate and drain or at their base and emitter and collector, e.g. in a cascode dif amp, only those forming the composite common source transistor or the composite common emitter transistor respectively
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Mram Or Spin Memory Techniques (AREA)
Description
212、214、216 第1のサブ差動トランジスタ
220、420、520 第2の差動トランジスタ
250、550 制御回路要素
522、524 第2のサブ差動トランジスタ
Claims (10)
- 第1の差動入力を受信する第1の差動回路と、
第2の差動入力を受信する第2の差動回路と、
前記第1の差動入力と前記第2の差動入力との差に比例した振幅を有する差動増幅器出力と、
制御回路要素
を備え、
前記第1の差動回路が、複数の第1のサブ差動トランジスタを有し、該第1のサブ差動トランジスタのゲートは前記第1の差動入力を受信し、該第1のサブ差動トランジスタの各々に、調整可能なバック・ゲート・バイアスがかけられ、前記複数の第1のサブ差動トランジスタの各々が異なるオフセット調整感度を提供し、
前記制御回路要素が、前記第1のサブ差動トランジスタのそれぞれの前記調整可能なバック・ゲート・バイアスに接続されて、前記差動増幅器出力のオフセット・エラーを低減することからなる、オフセット調整可能な差動増幅器。 - 前記第1のサブ差動トランジスタ(212、214、216)のそれぞれが、他の第1のサブ差動トランジスタのそれぞれとは異なる物理的寸法を有することからなる、請求項1に記載のオフセット調整可能な差動増幅器。
- 前記第1のサブ差動トランジスタ(212、214、216)に、物理的寸法が漸増する第1のサブ差動トランジスタが含まれる、請求項2に記載のオフセット調整可能な差動増幅器。
- 前記物理的寸法が漸増する第1のサブ差動トランジスタのそれぞれが、それに先行する第1のサブ差動トランジスタの物理的寸法の約2倍の寸法を有する、請求項3に記載のオフセット調整可能な差動増幅器。
- 前記物理的寸法が漸増する第1のサブ差動トランジスタのそれぞれが、それに先行する第1のサブ差動トランジスタの物理的寸法の約10倍の寸法を有する、請求項3に記載のオフセット調整可能な差動増幅器。
- 前記第2の差動回路に、調整可能なバック・ゲート・バイアスがかけられる、請求項1に記載のオフセット調整可能な差動増幅器。
- 前記第2の差動回路が、
複数の第2のサブ差動トランジスタ(522、524)であって、それぞれに、調整可能なバック・ゲート・バイアスがかけられることからなる、複数の第2のサブ差動トランジスタを備え、
前記制御回路要素(550)が、前記第2のサブ差動トランジスタのそれぞれの前記調整可能なバック・ゲート・バイアスに接続されて、前記差動増幅器出力のオフセット・エラーを低減することからなる、請求項1に記載のオフセット調整可能な差動増幅器。 - 前記第2のサブ差動トランジスタのそれぞれが、他の第2のサブ差動トランジスタのそれぞれとは異なる物理的寸法を有する、請求項7に記載のオフセット調整可能な差動増幅器。
- 前記第2のサブ差動トランジスタに、物理的寸法が漸増する第2のサブ差動トランジスタが含まれる、請求項8に記載のオフセット調整可能な差動増幅器。
- 前記物理的寸法が漸増する第2のサブ差動トランジスタのそれぞれが、それに先行する第2のサブ差動トランジスタの物理的寸法の約2倍の寸法を有する、請求項9に記載のオフセット調整可能な差動増幅器。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/350,398 US6807118B2 (en) | 2003-01-23 | 2003-01-23 | Adjustable offset differential amplifier |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2004229303A JP2004229303A (ja) | 2004-08-12 |
JP2004229303A5 JP2004229303A5 (ja) | 2005-05-26 |
JP4031447B2 true JP4031447B2 (ja) | 2008-01-09 |
Family
ID=32594940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004015416A Expired - Fee Related JP4031447B2 (ja) | 2003-01-23 | 2004-01-23 | オフセット調整可能な差動増幅器 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6807118B2 (ja) |
EP (1) | EP1441438A1 (ja) |
JP (1) | JP4031447B2 (ja) |
CN (1) | CN1518211A (ja) |
TW (1) | TW200414673A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8587372B2 (en) | 2010-05-31 | 2013-11-19 | Panasonic Corporation | Multi-input differential amplifier and light emitting element driving device |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6879929B2 (en) * | 2002-10-31 | 2005-04-12 | Sun Microsystems | Sense amplifier thermal correction scheme |
US7130235B2 (en) * | 2004-09-03 | 2006-10-31 | Hewlett-Packard Development Company, L.P. | Method and apparatus for a sense amplifier |
KR100678470B1 (ko) * | 2005-01-19 | 2007-02-02 | 삼성전자주식회사 | 차동 출력 드라이버 및 이를 구비한 반도체 장치 |
US7397288B2 (en) * | 2005-03-21 | 2008-07-08 | Semiconductor Components Industries, L.L.C. | Fan out buffer and method therefor |
US7333379B2 (en) * | 2006-01-12 | 2008-02-19 | International Business Machines Corporation | Balanced sense amplifier circuits with adjustable transistor body bias |
US7603084B2 (en) * | 2006-02-03 | 2009-10-13 | Wionics Technologies, Inc. | Method and apparatus for DC offset calibration |
KR100735754B1 (ko) * | 2006-02-03 | 2007-07-06 | 삼성전자주식회사 | 센스 앰프 플립 플롭 |
US20100329157A1 (en) * | 2009-06-25 | 2010-12-30 | Nanoamp Solutions Inc. (Cayman) | Even-Order Harmonics Calibration |
JP5493541B2 (ja) * | 2009-07-24 | 2014-05-14 | 凸版印刷株式会社 | 評価システム及び評価方法 |
CN101777375B (zh) * | 2010-03-10 | 2013-04-24 | 上海宏力半导体制造有限公司 | 一种感应放大器的匹配方法 |
TW201134088A (en) | 2010-03-31 | 2011-10-01 | Sunplus Technology Co Ltd | Differential offset calibration circuit |
US9159381B2 (en) | 2012-05-04 | 2015-10-13 | Qualcomm Incorporated | Tunable reference circuit |
JP6106045B2 (ja) * | 2013-03-22 | 2017-03-29 | 株式会社東芝 | 受光回路 |
US9496012B2 (en) | 2013-09-27 | 2016-11-15 | Cavium, Inc. | Method and apparatus for reference voltage calibration in a single-ended receiver |
US9413568B2 (en) | 2013-09-27 | 2016-08-09 | Cavium, Inc. | Method and apparatus for calibrating an input interface |
US9087567B2 (en) * | 2013-09-27 | 2015-07-21 | Cavium, Inc. | Method and apparatus for amplifier offset calibration |
JP5979160B2 (ja) * | 2014-01-06 | 2016-08-24 | 株式会社村田製作所 | 増幅器 |
US9601167B1 (en) * | 2015-03-02 | 2017-03-21 | Michael C. Stephens, Jr. | Semiconductor device having dual-gate transistors and calibration circuitry |
US9799395B2 (en) * | 2015-11-30 | 2017-10-24 | Texas Instruments Incorporated | Sense amplifier in low power and high performance SRAM |
KR102486764B1 (ko) * | 2015-12-16 | 2023-01-11 | 에스케이하이닉스 주식회사 | 차동 증폭기 회로 및 그를 포함하는 반도체 메모리 장치 |
US9911501B2 (en) * | 2016-05-24 | 2018-03-06 | Silicon Storage Technology, Inc. | Sensing amplifier comprising a built-in sensing offset for flash memory devices |
JP7242124B2 (ja) * | 2018-07-26 | 2023-03-20 | エイブリック株式会社 | 電圧検出回路、半導体装置及び製造方法 |
TWI822219B (zh) * | 2022-01-25 | 2023-11-11 | 立錡科技股份有限公司 | 具有低校正期間的操作電路與其中之校正方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4987327A (en) * | 1989-05-30 | 1991-01-22 | Motorola, Inc. | Apparatus for adjusting DC offset voltage |
US5568438A (en) * | 1995-07-18 | 1996-10-22 | Analog Devices, Inc. | Sense amplifier with offset autonulling |
US6262625B1 (en) | 1999-10-29 | 2001-07-17 | Hewlett-Packard Co | Operational amplifier with digital offset calibration |
JP2000049546A (ja) * | 1998-07-28 | 2000-02-18 | Mitsubishi Electric Corp | オフセット調整装置 |
US6388521B1 (en) * | 2000-09-22 | 2002-05-14 | National Semiconductor Corporation | MOS differential amplifier with offset compensation |
US6586989B2 (en) * | 2001-11-06 | 2003-07-01 | Hewlett-Packard Development Company, L.P. | Nonlinear digital differential amplifier offset calibration |
US6674679B1 (en) * | 2002-10-01 | 2004-01-06 | Hewlett-Packard Development Company, L.P. | Adjustable current mode differential amplifier for multiple bias point sensing of MRAM having equi-potential isolation |
-
2003
- 2003-01-23 US US10/350,398 patent/US6807118B2/en not_active Expired - Lifetime
- 2003-07-31 TW TW092120980A patent/TW200414673A/zh unknown
- 2003-12-16 EP EP03257915A patent/EP1441438A1/en not_active Withdrawn
- 2003-12-23 CN CNA2003101220710A patent/CN1518211A/zh active Pending
-
2004
- 2004-01-23 JP JP2004015416A patent/JP4031447B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8587372B2 (en) | 2010-05-31 | 2013-11-19 | Panasonic Corporation | Multi-input differential amplifier and light emitting element driving device |
Also Published As
Publication number | Publication date |
---|---|
CN1518211A (zh) | 2004-08-04 |
EP1441438A1 (en) | 2004-07-28 |
US20040145957A1 (en) | 2004-07-29 |
JP2004229303A (ja) | 2004-08-12 |
TW200414673A (en) | 2004-08-01 |
US6807118B2 (en) | 2004-10-19 |
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