JP2006093330A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2006093330A
JP2006093330A JP2004275565A JP2004275565A JP2006093330A JP 2006093330 A JP2006093330 A JP 2006093330A JP 2004275565 A JP2004275565 A JP 2004275565A JP 2004275565 A JP2004275565 A JP 2004275565A JP 2006093330 A JP2006093330 A JP 2006093330A
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JP
Japan
Prior art keywords
etching stopper
film
etching
stopper film
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004275565A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006093330A5 (https=
Inventor
Katsuhiro Uesugi
勝洋 上杉
Katsuo Katayama
克生 片山
Katsunao Sakai
克尚 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004275565A priority Critical patent/JP2006093330A/ja
Priority to TW094131784A priority patent/TW200618177A/zh
Priority to US11/229,550 priority patent/US7301237B2/en
Priority to KR1020050087804A priority patent/KR20060051496A/ko
Priority to CN200910139117A priority patent/CN101546748A/zh
Priority to CNB2005101063761A priority patent/CN100499068C/zh
Publication of JP2006093330A publication Critical patent/JP2006093330A/ja
Priority to US11/907,438 priority patent/US7465662B2/en
Publication of JP2006093330A5 publication Critical patent/JP2006093330A5/ja
Priority to US12/273,795 priority patent/US20090137114A1/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP2004275565A 2004-09-22 2004-09-22 半導体装置およびその製造方法 Pending JP2006093330A (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2004275565A JP2006093330A (ja) 2004-09-22 2004-09-22 半導体装置およびその製造方法
TW094131784A TW200618177A (en) 2004-09-22 2005-09-15 Semiconductor device and manufacturing method thereof
US11/229,550 US7301237B2 (en) 2004-09-22 2005-09-20 Semiconductor device
KR1020050087804A KR20060051496A (ko) 2004-09-22 2005-09-21 반도체 장치 및 그 제조방법
CN200910139117A CN101546748A (zh) 2004-09-22 2005-09-22 半导体装置及其制造方法
CNB2005101063761A CN100499068C (zh) 2004-09-22 2005-09-22 半导体装置及其制造方法
US11/907,438 US7465662B2 (en) 2004-09-22 2007-10-12 Method of making semiconductor device
US12/273,795 US20090137114A1 (en) 2004-09-22 2008-11-19 Method of making semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004275565A JP2006093330A (ja) 2004-09-22 2004-09-22 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2006093330A true JP2006093330A (ja) 2006-04-06
JP2006093330A5 JP2006093330A5 (https=) 2007-11-01

Family

ID=36074618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004275565A Pending JP2006093330A (ja) 2004-09-22 2004-09-22 半導体装置およびその製造方法

Country Status (5)

Country Link
US (3) US7301237B2 (https=)
JP (1) JP2006093330A (https=)
KR (1) KR20060051496A (https=)
CN (2) CN100499068C (https=)
TW (1) TW200618177A (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070293034A1 (en) * 2006-06-15 2007-12-20 Macronix International Co., Ltd. Unlanded via process without plasma damage
US9391020B2 (en) * 2014-03-31 2016-07-12 Stmicroelectronics, Inc. Interconnect structure having large self-aligned vias

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2953188B2 (ja) 1992-04-24 1999-09-27 日本電気株式会社 半導体装置の製造方法
JP3297220B2 (ja) * 1993-10-29 2002-07-02 株式会社東芝 半導体装置の製造方法および半導体装置
JPH097970A (ja) 1995-06-21 1997-01-10 Sanyo Electric Co Ltd 半導体装置の製造方法
TW337608B (en) * 1997-10-29 1998-08-01 United Microelectronics Corp Process for producing unlanded via
JP2000294631A (ja) 1999-04-05 2000-10-20 Mitsubishi Electric Corp 半導体装置及びその製造方法
KR100303366B1 (ko) * 1999-06-29 2001-11-01 박종섭 반도체 소자의 배선 형성방법
CN1224092C (zh) * 2000-04-28 2005-10-19 东京毅力科创株式会社 具有低介电膜的半导体器件及其制造方法
JP2002009152A (ja) * 2000-06-21 2002-01-11 Nec Corp 半導体装置及びその製造方法
US20030148618A1 (en) * 2002-02-07 2003-08-07 Applied Materials, Inc. Selective metal passivated copper interconnect with zero etch stops

Also Published As

Publication number Publication date
US20080045006A1 (en) 2008-02-21
US7301237B2 (en) 2007-11-27
CN101546748A (zh) 2009-09-30
KR20060051496A (ko) 2006-05-19
US20090137114A1 (en) 2009-05-28
CN1758425A (zh) 2006-04-12
CN100499068C (zh) 2009-06-10
TW200618177A (en) 2006-06-01
US7465662B2 (en) 2008-12-16
US20060063372A1 (en) 2006-03-23

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