JP2006086533A5 - - Google Patents

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Publication number
JP2006086533A5
JP2006086533A5 JP2005266157A JP2005266157A JP2006086533A5 JP 2006086533 A5 JP2006086533 A5 JP 2006086533A5 JP 2005266157 A JP2005266157 A JP 2005266157A JP 2005266157 A JP2005266157 A JP 2005266157A JP 2006086533 A5 JP2006086533 A5 JP 2006086533A5
Authority
JP
Japan
Prior art keywords
photoresist
flattened
guard ring
creating
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005266157A
Other languages
English (en)
Japanese (ja)
Other versions
JP4944414B2 (ja
JP2006086533A (ja
Filing date
Publication date
Priority claimed from US10/941,665 external-priority patent/US7253012B2/en
Application filed filed Critical
Publication of JP2006086533A publication Critical patent/JP2006086533A/ja
Publication of JP2006086533A5 publication Critical patent/JP2006086533A5/ja
Application granted granted Critical
Publication of JP4944414B2 publication Critical patent/JP4944414B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2005266157A 2004-09-14 2005-09-14 向上した一致性のためのガードリング Expired - Fee Related JP4944414B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/941,665 US7253012B2 (en) 2004-09-14 2004-09-14 Guard ring for improved matching
US10/941665 2004-09-14

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011254917A Division JP2012060152A (ja) 2004-09-14 2011-11-22 向上した一致性のためのガードリング

Publications (3)

Publication Number Publication Date
JP2006086533A JP2006086533A (ja) 2006-03-30
JP2006086533A5 true JP2006086533A5 (enExample) 2008-05-01
JP4944414B2 JP4944414B2 (ja) 2012-05-30

Family

ID=36034618

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2005266157A Expired - Fee Related JP4944414B2 (ja) 2004-09-14 2005-09-14 向上した一致性のためのガードリング
JP2011254917A Withdrawn JP2012060152A (ja) 2004-09-14 2011-11-22 向上した一致性のためのガードリング

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011254917A Withdrawn JP2012060152A (ja) 2004-09-14 2011-11-22 向上した一致性のためのガードリング

Country Status (5)

Country Link
US (2) US7253012B2 (enExample)
JP (2) JP4944414B2 (enExample)
KR (2) KR101215425B1 (enExample)
CN (1) CN1750252B (enExample)
TW (1) TWI368258B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7958467B2 (en) * 2006-06-20 2011-06-07 Adtran, Inc. Deterministic system and method for generating wiring layouts for integrated circuits
US7992117B2 (en) * 2006-06-20 2011-08-02 Adtran, Inc. System and method for designing a common centroid layout for an integrated circuit
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
CN102339826B (zh) * 2011-11-01 2013-01-16 矽力杰半导体技术(杭州)有限公司 一种器件匹配的集成电路及其设计方法
US8846302B2 (en) * 2012-02-01 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method and tool for forming the semiconductor structure
US8658444B2 (en) 2012-05-16 2014-02-25 International Business Machines Corporation Semiconductor active matrix on buried insulator
US9202000B1 (en) * 2014-09-30 2015-12-01 Cadence Design Systems, Inc. Implementing designs of guard ring and fill structures from simple unit cells

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161834A (ja) * 1983-03-07 1984-09-12 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS61206262A (ja) * 1985-03-11 1986-09-12 Shindengen Electric Mfg Co Ltd 高耐圧プレ−ナ型半導体装置
US4988636A (en) * 1990-01-29 1991-01-29 International Business Machines Corporation Method of making bit stack compatible input/output circuits
EP0538507B1 (de) * 1991-10-22 1996-12-27 Deutsche ITT Industries GmbH Schutzschaltung für Anschlusskontakte von monolithisch integrierten Schaltungen
JP3223490B2 (ja) * 1993-06-30 2001-10-29 ソニー株式会社 半導体集積回路製造方法
US5965925A (en) 1997-10-22 1999-10-12 Artisan Components, Inc. Integrated circuit layout methods and layout structures
JP3998454B2 (ja) * 2001-10-31 2007-10-24 株式会社東芝 電力用半導体装置
JP2003142583A (ja) * 2001-11-01 2003-05-16 Seiko Epson Corp 半導体装置及びその設計方法
US6646509B2 (en) 2002-01-23 2003-11-11 Broadcom Corporation Layout technique for matched resistors on an integrated circuit substrate
US7393755B2 (en) 2002-06-07 2008-07-01 Cadence Design Systems, Inc. Dummy fill for integrated circuits
JP4353685B2 (ja) * 2002-09-18 2009-10-28 株式会社ルネサステクノロジ 半導体装置
US7148089B2 (en) * 2004-03-01 2006-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper fuse links

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