CN1750252B - 用于提高匹配的防护环 - Google Patents

用于提高匹配的防护环 Download PDF

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Publication number
CN1750252B
CN1750252B CN2005101096430A CN200510109643A CN1750252B CN 1750252 B CN1750252 B CN 1750252B CN 2005101096430 A CN2005101096430 A CN 2005101096430A CN 200510109643 A CN200510109643 A CN 200510109643A CN 1750252 B CN1750252 B CN 1750252B
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CN
China
Prior art keywords
guard ring
photoresist
thickness
devices
leveling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2005101096430A
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English (en)
Chinese (zh)
Other versions
CN1750252A (zh
Inventor
丹尼尔·C.·克尔
罗斯科·T.·卢斯
米奇立·M.·加米森
艾伦·S.·陈
威廉·A.·拉塞尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of CN1750252A publication Critical patent/CN1750252A/zh
Application granted granted Critical
Publication of CN1750252B publication Critical patent/CN1750252B/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)
CN2005101096430A 2004-09-14 2005-09-14 用于提高匹配的防护环 Expired - Lifetime CN1750252B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/941,665 US7253012B2 (en) 2004-09-14 2004-09-14 Guard ring for improved matching
US10/941,665 2004-09-14

Publications (2)

Publication Number Publication Date
CN1750252A CN1750252A (zh) 2006-03-22
CN1750252B true CN1750252B (zh) 2012-05-30

Family

ID=36034618

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2005101096430A Expired - Lifetime CN1750252B (zh) 2004-09-14 2005-09-14 用于提高匹配的防护环

Country Status (5)

Country Link
US (2) US7253012B2 (enExample)
JP (2) JP4944414B2 (enExample)
KR (2) KR101215425B1 (enExample)
CN (1) CN1750252B (enExample)
TW (1) TWI368258B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7992117B2 (en) * 2006-06-20 2011-08-02 Adtran, Inc. System and method for designing a common centroid layout for an integrated circuit
US7958467B2 (en) * 2006-06-20 2011-06-07 Adtran, Inc. Deterministic system and method for generating wiring layouts for integrated circuits
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
CN102339826B (zh) * 2011-11-01 2013-01-16 矽力杰半导体技术(杭州)有限公司 一种器件匹配的集成电路及其设计方法
US8846302B2 (en) * 2012-02-01 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method and tool for forming the semiconductor structure
US8658444B2 (en) * 2012-05-16 2014-02-25 International Business Machines Corporation Semiconductor active matrix on buried insulator
US9202000B1 (en) * 2014-09-30 2015-12-01 Cadence Design Systems, Inc. Implementing designs of guard ring and fill structures from simple unit cells

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161834A (ja) * 1983-03-07 1984-09-12 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS61206262A (ja) * 1985-03-11 1986-09-12 Shindengen Electric Mfg Co Ltd 高耐圧プレ−ナ型半導体装置
US4988636A (en) * 1990-01-29 1991-01-29 International Business Machines Corporation Method of making bit stack compatible input/output circuits
DE59108436D1 (de) * 1991-10-22 1997-02-06 Itt Ind Gmbh Deutsche Schutzschaltung für Anschlusskontakte von monolithisch integrierten Schaltungen
JP3223490B2 (ja) * 1993-06-30 2001-10-29 ソニー株式会社 半導体集積回路製造方法
US5965925A (en) * 1997-10-22 1999-10-12 Artisan Components, Inc. Integrated circuit layout methods and layout structures
JP3998454B2 (ja) * 2001-10-31 2007-10-24 株式会社東芝 電力用半導体装置
JP2003142583A (ja) * 2001-11-01 2003-05-16 Seiko Epson Corp 半導体装置及びその設計方法
US6646509B2 (en) * 2002-01-23 2003-11-11 Broadcom Corporation Layout technique for matched resistors on an integrated circuit substrate
US7393755B2 (en) * 2002-06-07 2008-07-01 Cadence Design Systems, Inc. Dummy fill for integrated circuits
JP4353685B2 (ja) * 2002-09-18 2009-10-28 株式会社ルネサステクノロジ 半導体装置
US7148089B2 (en) * 2004-03-01 2006-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper fuse links

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JP特开平5-251640A 1993.09.28
JP特开平7-3668A 1995.01.06

Also Published As

Publication number Publication date
TWI368258B (en) 2012-07-11
KR20120023172A (ko) 2012-03-12
KR101215425B1 (ko) 2012-12-26
US20070212873A1 (en) 2007-09-13
JP2012060152A (ja) 2012-03-22
US7407824B2 (en) 2008-08-05
CN1750252A (zh) 2006-03-22
KR20060051300A (ko) 2006-05-19
US20060057840A1 (en) 2006-03-16
JP2006086533A (ja) 2006-03-30
US7253012B2 (en) 2007-08-07
TW200633007A (en) 2006-09-16
JP4944414B2 (ja) 2012-05-30

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C06 Publication
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SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
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C56 Change in the name or address of the patentee

Owner name: AGERE SYSTEMS GUARDIAN CORP.

Free format text: FORMER NAME: EGREE SYSTEM CO. LTD.

CP03 Change of name, title or address

Address after: Delaware

Patentee after: Agere Systems Inc.

Address before: New jersey, USA

Patentee before: AGERE SYSTEMS Inc.

C41 Transfer of patent application or patent right or utility model
C56 Change in the name or address of the patentee
CP02 Change in the address of a patent holder

Address after: American Pennsylvania

Patentee after: Agere Systems Inc.

Address before: Delaware

Patentee before: Agere Systems Inc.

TR01 Transfer of patent right

Effective date of registration: 20160918

Address after: Singapore Singapore

Patentee after: Avago Technologies General IP (Singapore) Pte. Ltd.

Address before: American Pennsylvania

Patentee before: Agere Systems Inc.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20120530