JP4944414B2 - 向上した一致性のためのガードリング - Google Patents
向上した一致性のためのガードリング Download PDFInfo
- Publication number
- JP4944414B2 JP4944414B2 JP2005266157A JP2005266157A JP4944414B2 JP 4944414 B2 JP4944414 B2 JP 4944414B2 JP 2005266157 A JP2005266157 A JP 2005266157A JP 2005266157 A JP2005266157 A JP 2005266157A JP 4944414 B2 JP4944414 B2 JP 4944414B2
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- JP
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- Prior art keywords
- guard ring
- photoresist
- devices
- thickness
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/95—Multilayer mask including nonradiation sensitive layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
Description
「Design of Matching Test Structures」,H.P.Tuinhout,Proc.IEEE 1994 Int’l.Conference on Microelectronic Test Structures、第7巻、21〜23頁、1994年3月 Peter Van Zantによる「Microchip Fabrication」、第3版、1997年、McGraw Hill(Zant関連)
新規的であると考えられる本発明の特徴は添付の特許請求項で特定して述べられる。しかしながら、本発明自体はその構造および操作の方法の両方で、以下の説明および添付の図面を参照することによって最もよく理解されることが可能である。
・各々のウェハが例えばスピンコーティングによって表面に塗布されたフォトレジスト材料を有する。
・ウェハがマスクを備えて紫外光のようなエネルギー源に暴露され、フォトレジストを露光してフォトレジスト上に所望のパターンを作り出す。
・現像液を加えることによってフォトレジストが現像される。
・適切なリソグラフィまたは固定化方法によってパターン(すなわち画像)が定着処理される。
・各々のウェハがエッチングされる。
・後になって残ったフォトレジストが除去される。
a.第1の特定の領域の周囲に平担化ガードリングを形成する工程。これは通常、特定の加工工程中にウェハ表面全体にわたって他のデバイスに特徴構造を形成する間に為され、一度に多数の平担化ガードリングを形成する処理を含むことが可能である。例えば、限定はしないがこの形成は当該技術で実践されるような堆積およびそれに関連する工程によって達成されることが可能である。気付かれるように、ガードリングは複数の層で形成されることが可能である。
b.ウェハの上にフォトレジストを塗布する工程。スピンコーティングがフォトレジストを塗布する通常の方式であるが、しかし現在または今後に当業者に知られるいずれの手段も使用されることが可能である。
Claims (4)
- 半導体ウェハ上に集積回路を作製の際に、前記ウェハ上のパターニングされた回路の封鎖領域の中でフォトレジスト厚さのばらつきを低減する方法であって、
a.半導体ウェハの第1の特定領域の周りに、前記第1の特定領域内にフォトレジストを保持するのに十分な高さまで第1の平担化ガードリングを形成する工程と、
b.前記第1の平坦化ガードリングの上且つ前記第1の特定領域内にフォトレジストを塗布する工程とを含み、前記フォトレジストは前記特定領域内の空き容積を満たし、さらに、
c.前記フォトレジスト用いて前記第1の特定領域に1つ以上のデバイスを作製する工程を含む、方法。 - 前記ガードリングの内側に2つ以上のデバイスを共通重心パターンで作製する工程を追加的に含む、請求項1に記載の方法。
- 前記第1の特定領域のフォトレジストの厚さの均一性に対する周りの構造の高さの影響を低下させるのに十分な高さに前記第1の平担化ガードリングを形成する、請求項1に記載の方法。
- 少なくとも1つの追加の特定領域の周りに少なくとも1つの追加の平担化ガードリングを形成する工程と、2つ以上のデバイスのアレイを前記少なくとも1つの追加の特定領域に作製する工程とを追加的に含む、請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/941,665 US7253012B2 (en) | 2004-09-14 | 2004-09-14 | Guard ring for improved matching |
US10/941665 | 2004-09-14 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011254917A Division JP2012060152A (ja) | 2004-09-14 | 2011-11-22 | 向上した一致性のためのガードリング |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006086533A JP2006086533A (ja) | 2006-03-30 |
JP2006086533A5 JP2006086533A5 (ja) | 2008-05-01 |
JP4944414B2 true JP4944414B2 (ja) | 2012-05-30 |
Family
ID=36034618
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005266157A Expired - Fee Related JP4944414B2 (ja) | 2004-09-14 | 2005-09-14 | 向上した一致性のためのガードリング |
JP2011254917A Withdrawn JP2012060152A (ja) | 2004-09-14 | 2011-11-22 | 向上した一致性のためのガードリング |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011254917A Withdrawn JP2012060152A (ja) | 2004-09-14 | 2011-11-22 | 向上した一致性のためのガードリング |
Country Status (5)
Country | Link |
---|---|
US (2) | US7253012B2 (ja) |
JP (2) | JP4944414B2 (ja) |
KR (2) | KR101215425B1 (ja) |
CN (1) | CN1750252B (ja) |
TW (1) | TWI368258B (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7958467B2 (en) * | 2006-06-20 | 2011-06-07 | Adtran, Inc. | Deterministic system and method for generating wiring layouts for integrated circuits |
US7992117B2 (en) * | 2006-06-20 | 2011-08-02 | Adtran, Inc. | System and method for designing a common centroid layout for an integrated circuit |
KR101782503B1 (ko) * | 2011-05-18 | 2017-09-28 | 삼성전자 주식회사 | 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법 |
CN102339826B (zh) * | 2011-11-01 | 2013-01-16 | 矽力杰半导体技术(杭州)有限公司 | 一种器件匹配的集成电路及其设计方法 |
US8846302B2 (en) * | 2012-02-01 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method and tool for forming the semiconductor structure |
US8658444B2 (en) * | 2012-05-16 | 2014-02-25 | International Business Machines Corporation | Semiconductor active matrix on buried insulator |
US9202000B1 (en) * | 2014-09-30 | 2015-12-01 | Cadence Design Systems, Inc. | Implementing designs of guard ring and fill structures from simple unit cells |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59161834A (ja) * | 1983-03-07 | 1984-09-12 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS61206262A (ja) * | 1985-03-11 | 1986-09-12 | Shindengen Electric Mfg Co Ltd | 高耐圧プレ−ナ型半導体装置 |
US4988636A (en) * | 1990-01-29 | 1991-01-29 | International Business Machines Corporation | Method of making bit stack compatible input/output circuits |
DE59108436D1 (de) * | 1991-10-22 | 1997-02-06 | Itt Ind Gmbh Deutsche | Schutzschaltung für Anschlusskontakte von monolithisch integrierten Schaltungen |
JP3223490B2 (ja) * | 1993-06-30 | 2001-10-29 | ソニー株式会社 | 半導体集積回路製造方法 |
US5965925A (en) * | 1997-10-22 | 1999-10-12 | Artisan Components, Inc. | Integrated circuit layout methods and layout structures |
JP3998454B2 (ja) * | 2001-10-31 | 2007-10-24 | 株式会社東芝 | 電力用半導体装置 |
JP2003142583A (ja) * | 2001-11-01 | 2003-05-16 | Seiko Epson Corp | 半導体装置及びその設計方法 |
US6646509B2 (en) * | 2002-01-23 | 2003-11-11 | Broadcom Corporation | Layout technique for matched resistors on an integrated circuit substrate |
US7393755B2 (en) * | 2002-06-07 | 2008-07-01 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
JP4353685B2 (ja) * | 2002-09-18 | 2009-10-28 | 株式会社ルネサステクノロジ | 半導体装置 |
US7148089B2 (en) * | 2004-03-01 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming copper fuse links |
-
2004
- 2004-09-14 US US10/941,665 patent/US7253012B2/en active Active
-
2005
- 2005-08-24 TW TW094128975A patent/TWI368258B/zh not_active IP Right Cessation
- 2005-09-14 CN CN2005101096430A patent/CN1750252B/zh active Active
- 2005-09-14 KR KR1020050085840A patent/KR101215425B1/ko active IP Right Grant
- 2005-09-14 JP JP2005266157A patent/JP4944414B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-15 US US11/748,569 patent/US7407824B2/en active Active
-
2011
- 2011-11-22 JP JP2011254917A patent/JP2012060152A/ja not_active Withdrawn
-
2012
- 2012-02-27 KR KR1020120019484A patent/KR20120023172A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JP2012060152A (ja) | 2012-03-22 |
CN1750252A (zh) | 2006-03-22 |
TWI368258B (en) | 2012-07-11 |
US7253012B2 (en) | 2007-08-07 |
KR101215425B1 (ko) | 2012-12-26 |
JP2006086533A (ja) | 2006-03-30 |
KR20060051300A (ko) | 2006-05-19 |
KR20120023172A (ko) | 2012-03-12 |
TW200633007A (en) | 2006-09-16 |
CN1750252B (zh) | 2012-05-30 |
US7407824B2 (en) | 2008-08-05 |
US20060057840A1 (en) | 2006-03-16 |
US20070212873A1 (en) | 2007-09-13 |
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