JP2006086486A - 不揮発性メモリ素子のゲート電極形成方法 - Google Patents
不揮発性メモリ素子のゲート電極形成方法 Download PDFInfo
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- JP2006086486A JP2006086486A JP2004371269A JP2004371269A JP2006086486A JP 2006086486 A JP2006086486 A JP 2006086486A JP 2004371269 A JP2004371269 A JP 2004371269A JP 2004371269 A JP2004371269 A JP 2004371269A JP 2006086486 A JP2006086486 A JP 2006086486A
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- 238000000034 method Methods 0.000 title claims abstract description 89
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 68
- 238000005530 etching Methods 0.000 claims abstract description 65
- 239000000654 additive Substances 0.000 claims abstract description 17
- 230000000996 additive effect Effects 0.000 claims abstract description 17
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Drying Of Semiconductors (AREA)
Abstract
【解決手段】トンネル酸化膜111、フローティングゲート用第1ポリシリコン膜113、誘電体膜114及びコントロールゲート用第2ポリシリコン膜115の形成された半導体基板を準備する段階と、メインエッチングガスにカーボン含有添加ガスを追加させた第1エッチング工程を行い、前記第2ポリシリコン膜、前記誘電体膜および前記第1ポリシリコン膜の一部をパターニングする段階と、前記添加ガスの供給を遮断した後、前記メインエッチングガスのみを用いた第2エッチング工程を行って、パターニングされずに残留した前記第1ポリシリコン膜と前記トンネル酸化膜をパターニングする段階とを含む。
【選択図】図3
Description
111 トンネル酸化膜
113 第2ポリシリコン膜
114 誘電体膜
115 第3ポリシリコン膜
116 金属シリサイド層
117 ハードマスク
Claims (11)
- (a)トンネル酸化膜、フローティングゲート用第1ポリシリコン膜、誘電体膜及びコントロールゲート用第2ポリシリコン膜の形成された半導体基板を準備する段階と、
(b)メインエッチングガスにカーボン含有添加ガスを追加させた第1エッチング工程を行い、前記第2ポリシリコン膜、前記誘電体膜および前記第1ポリシリコン膜の一部をパターニングする段階と、
(c)前記添加ガスの供給を遮断した後、前記メインエッチングガスのみを用いた第2エッチング工程を行って、パターニングされずに残留した前記第1ポリシリコン膜と前記トンネル酸化膜をパターニングする段階とを含む不揮発性メモリ素子のゲート電極形成方法。 - 前記メインエッチングガスはCl2またはHBrを使用することを特徴とする請求項1記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記添加ガスは前記メインエッチングガスの0.5倍〜2倍供給されることを特徴とする請求項1記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記添加ガスはCF4、CHF3、C2F6、CH2F2、C4F8、C3F8、C5F8及びCH3Fのいずれか一つであり、或いはこれらが少なくとも2以上混合された混合ガスであることを特徴とする請求項1または3記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記(b)段階で前記第1エッチング工程時に前記添加ガスのカーボンによってパターニングされて露出される前記第2ポリシリコン膜、前記誘電体膜および前記第1ポリシリコン膜の一部にはパッシベーション層が形成されることを特徴とする請求項1記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記(a)段階で前記第2ポリシリコン膜上には金属シリサイド層がさらに形成される段階をさらに含むことを特徴とする請求項1記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記(b)段階の前に、前記金属シリサイド層はCl2またはSF6ガスを用いた第3エッチング工程によってエッチングされてパターニングされることを特徴とする請求項6記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記第1〜第3エッチング工程は同一のエッチングチャンバー内で行われることを特徴とする請求項7記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記(a)段階で金属シリサイド層上にはハードマスクが形成される段階をさらに含むことを特徴とする請求項6記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記ハードマスクは前記第1エッチング工程時にエッチングマスクとして機能することを特徴とする請求項6記載の不揮発性メモリ素子のゲート電極形成方法。
- 前記第1及び第2エッチング工程は同一のエッチングチャンバー内で行われることを特徴とする請求項1記載の不揮発性メモリ素子のゲート電極形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR2004-073679 | 2004-09-15 | ||
KR1020040073679A KR100616193B1 (ko) | 2004-09-15 | 2004-09-15 | 비휘발성 메모리 소자의 게이트 전극 형성방법 |
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JP2006086486A true JP2006086486A (ja) | 2006-03-30 |
JP4863616B2 JP4863616B2 (ja) | 2012-01-25 |
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JP2004371269A Expired - Fee Related JP4863616B2 (ja) | 2004-09-15 | 2004-12-22 | 不揮発性メモリ素子のゲート電極形成方法 |
Country Status (6)
Country | Link |
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US (1) | US7259063B2 (ja) |
JP (1) | JP4863616B2 (ja) |
KR (1) | KR100616193B1 (ja) |
CN (1) | CN100373552C (ja) |
DE (1) | DE102004060446B4 (ja) |
TW (1) | TWI265562B (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010263132A (ja) * | 2009-05-11 | 2010-11-18 | Hitachi High-Technologies Corp | ドライエッチング方法 |
US7989331B2 (en) | 2006-10-10 | 2011-08-02 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
US8586446B2 (en) | 2011-02-08 | 2013-11-19 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
KR101819744B1 (ko) | 2011-04-26 | 2018-01-18 | 에스케이하이닉스 주식회사 | 반도체 소자의 제조방법 |
CN110571151A (zh) * | 2019-09-02 | 2019-12-13 | 武汉新芯集成电路制造有限公司 | 多晶硅层的制作方法、闪存及其制作方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100810417B1 (ko) * | 2005-11-28 | 2008-03-04 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 게이트 형성 방법 |
US7589005B2 (en) * | 2006-09-29 | 2009-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming semiconductor structures and systems for forming semiconductor structures |
US7538034B2 (en) * | 2006-12-22 | 2009-05-26 | Qimonda Ag | Integrated circuit having a metal element |
KR101488417B1 (ko) | 2008-08-19 | 2015-01-30 | 삼성전자주식회사 | 전하의 측면 이동을 억제하는 메모리 소자 |
KR101683072B1 (ko) | 2010-09-13 | 2016-12-21 | 삼성전자 주식회사 | 반도체 소자의 형성 방법 |
Citations (5)
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JPS5951574A (ja) * | 1982-09-17 | 1984-03-26 | Mitsubishi Electric Corp | Mos形半導体不揮発性メモリ装置の製造方法 |
JPH02272776A (ja) * | 1989-04-14 | 1990-11-07 | Nec Corp | 半導体記憶装置の製造方法 |
JPH0846064A (ja) * | 1994-07-27 | 1996-02-16 | Nkk Corp | 不揮発性半導体メモリ装置 |
JP2002270585A (ja) * | 2001-03-08 | 2002-09-20 | Sharp Corp | 半導体装置の製造方法 |
JP2002359231A (ja) * | 2001-05-31 | 2002-12-13 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
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JP4683685B2 (ja) * | 2000-01-17 | 2011-05-18 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法、フラッシュメモリの製造方法、およびスタティックランダムアクセスメモリの製造方法 |
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KR100426486B1 (ko) * | 2001-12-22 | 2004-04-14 | 주식회사 하이닉스반도체 | 플래시 메모리 셀의 제조 방법 |
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-
2004
- 2004-09-15 KR KR1020040073679A patent/KR100616193B1/ko active IP Right Grant
- 2004-12-13 US US11/010,986 patent/US7259063B2/en active Active
- 2004-12-13 TW TW093138523A patent/TWI265562B/zh not_active IP Right Cessation
- 2004-12-14 DE DE102004060446A patent/DE102004060446B4/de not_active Expired - Fee Related
- 2004-12-22 JP JP2004371269A patent/JP4863616B2/ja not_active Expired - Fee Related
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2005
- 2005-01-20 CN CNB2005100055274A patent/CN100373552C/zh active Active
Patent Citations (5)
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JPS5951574A (ja) * | 1982-09-17 | 1984-03-26 | Mitsubishi Electric Corp | Mos形半導体不揮発性メモリ装置の製造方法 |
JPH02272776A (ja) * | 1989-04-14 | 1990-11-07 | Nec Corp | 半導体記憶装置の製造方法 |
JPH0846064A (ja) * | 1994-07-27 | 1996-02-16 | Nkk Corp | 不揮発性半導体メモリ装置 |
JP2002270585A (ja) * | 2001-03-08 | 2002-09-20 | Sharp Corp | 半導体装置の製造方法 |
JP2002359231A (ja) * | 2001-05-31 | 2002-12-13 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7989331B2 (en) | 2006-10-10 | 2011-08-02 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
US8815726B2 (en) | 2006-10-10 | 2014-08-26 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JP2010263132A (ja) * | 2009-05-11 | 2010-11-18 | Hitachi High-Technologies Corp | ドライエッチング方法 |
US8586446B2 (en) | 2011-02-08 | 2013-11-19 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
KR101819744B1 (ko) | 2011-04-26 | 2018-01-18 | 에스케이하이닉스 주식회사 | 반도체 소자의 제조방법 |
CN110571151A (zh) * | 2019-09-02 | 2019-12-13 | 武汉新芯集成电路制造有限公司 | 多晶硅层的制作方法、闪存及其制作方法 |
CN110571151B (zh) * | 2019-09-02 | 2021-10-26 | 武汉新芯集成电路制造有限公司 | 多晶硅层的制作方法、闪存及其制作方法 |
Also Published As
Publication number | Publication date |
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DE102004060446A1 (de) | 2006-03-30 |
TWI265562B (en) | 2006-11-01 |
US20060057805A1 (en) | 2006-03-16 |
CN1750235A (zh) | 2006-03-22 |
KR20060025295A (ko) | 2006-03-21 |
DE102004060446B4 (de) | 2011-05-12 |
JP4863616B2 (ja) | 2012-01-25 |
US7259063B2 (en) | 2007-08-21 |
TW200610038A (en) | 2006-03-16 |
CN100373552C (zh) | 2008-03-05 |
KR100616193B1 (ko) | 2006-08-25 |
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