JP2006049780A - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP2006049780A
JP2006049780A JP2004232454A JP2004232454A JP2006049780A JP 2006049780 A JP2006049780 A JP 2006049780A JP 2004232454 A JP2004232454 A JP 2004232454A JP 2004232454 A JP2004232454 A JP 2004232454A JP 2006049780 A JP2006049780 A JP 2006049780A
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JP
Japan
Prior art keywords
channel
channel transistor
wiring layer
main wiring
semiconductor integrated
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Pending
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JP2004232454A
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English (en)
Japanese (ja)
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JP2006049780A5 (enExample
Inventor
Minoru Yamagami
実 山上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP2004232454A priority Critical patent/JP2006049780A/ja
Priority to US11/194,683 priority patent/US7508238B2/en
Publication of JP2006049780A publication Critical patent/JP2006049780A/ja
Publication of JP2006049780A5 publication Critical patent/JP2006049780A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H10D89/105—Integrated device layouts adapted for thermal considerations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2004232454A 2004-08-09 2004-08-09 半導体集積回路装置 Pending JP2006049780A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004232454A JP2006049780A (ja) 2004-08-09 2004-08-09 半導体集積回路装置
US11/194,683 US7508238B2 (en) 2004-08-09 2005-08-02 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004232454A JP2006049780A (ja) 2004-08-09 2004-08-09 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2006049780A true JP2006049780A (ja) 2006-02-16
JP2006049780A5 JP2006049780A5 (enExample) 2007-08-30

Family

ID=35756574

Family Applications (1)

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JP2004232454A Pending JP2006049780A (ja) 2004-08-09 2004-08-09 半導体集積回路装置

Country Status (2)

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US (1) US7508238B2 (enExample)
JP (1) JP2006049780A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008244265A (ja) * 2007-03-28 2008-10-09 Ishizuka Electronics Corp マルチセル型定電流ダイオード
JP2010165969A (ja) * 2009-01-19 2010-07-29 Fujitsu Semiconductor Ltd 半導体装置の製造方法および半導体装置

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8667443B2 (en) * 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101903975B1 (ko) 2008-07-16 2018-10-04 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
IT1392501B1 (it) * 2008-12-30 2012-03-09 St Microelectronics Pvt Ltd Cella di base per implementazione di un ordine di modifica o engineering change order (eco)
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8234612B2 (en) * 2010-08-25 2012-07-31 International Business Machines Corporation Cone-aware spare cell placement using hypergraph connectivity analysis
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9236343B2 (en) 2013-05-03 2016-01-12 Blackcomb Design Automation Inc. Architecture of spare wiring structures for improved engineering change orders
CN113098493B (zh) * 2021-04-01 2023-05-30 长鑫存储技术有限公司 逻辑门电路结构
US20230307457A1 (en) * 2022-03-24 2023-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5858741A (ja) * 1981-10-05 1983-04-07 Nec Corp 集積回路装置
JPH04167544A (ja) * 1990-10-31 1992-06-15 Fujitsu Ltd 設計変更用セル及びこれを用いたレイアウト方法
JPH0997885A (ja) * 1995-09-28 1997-04-08 Denso Corp ゲートアレイ
JP2001352047A (ja) * 2000-06-05 2001-12-21 Oki Micro Design Co Ltd 半導体集積回路
JP2002319665A (ja) * 2000-09-21 2002-10-31 Matsushita Electric Ind Co Ltd Ｃｍｏｓ型基本セル及びこれを使用した半導体集積回路の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05198680A (ja) 1992-01-20 1993-08-06 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
JPH06216247A (ja) 1993-01-14 1994-08-05 Hitachi Ltd 半導体集積回路、及びその配線パターンの修正方法
JP2000236063A (ja) 1999-02-12 2000-08-29 Nec Corp 半導体集積回路
JP2000299382A (ja) 1999-04-13 2000-10-24 Matsushita Electric Ind Co Ltd 半導体集積回路用レイアウトセル
US6404226B1 (en) * 1999-09-21 2002-06-11 Lattice Semiconductor Corporation Integrated circuit with standard cell logic and spare gates
JP2004079138A (ja) * 2002-08-22 2004-03-11 Renesas Technology Corp 不揮発性半導体記憶装置
US7034384B2 (en) * 2004-04-13 2006-04-25 Faraday Technology Corp. Integrated circuit adapted for ECO and FIB debug

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5858741A (ja) * 1981-10-05 1983-04-07 Nec Corp 集積回路装置
JPH04167544A (ja) * 1990-10-31 1992-06-15 Fujitsu Ltd 設計変更用セル及びこれを用いたレイアウト方法
JPH0997885A (ja) * 1995-09-28 1997-04-08 Denso Corp ゲートアレイ
JP2001352047A (ja) * 2000-06-05 2001-12-21 Oki Micro Design Co Ltd 半導体集積回路
JP2002319665A (ja) * 2000-09-21 2002-10-31 Matsushita Electric Ind Co Ltd Ｃｍｏｓ型基本セル及びこれを使用した半導体集積回路の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008244265A (ja) * 2007-03-28 2008-10-09 Ishizuka Electronics Corp マルチセル型定電流ダイオード
JP2010165969A (ja) * 2009-01-19 2010-07-29 Fujitsu Semiconductor Ltd 半導体装置の製造方法および半導体装置

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Publication number Publication date
US20060027835A1 (en) 2006-02-09
US7508238B2 (en) 2009-03-24

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