IT1392501B1 - Cella di base per implementazione di un ordine di modifica o engineering change order (eco) - Google Patents

Cella di base per implementazione di un ordine di modifica o engineering change order (eco)

Info

Publication number
IT1392501B1
IT1392501B1 ITMI2008A002357A ITMI20082357A IT1392501B1 IT 1392501 B1 IT1392501 B1 IT 1392501B1 IT MI2008A002357 A ITMI2008A002357 A IT MI2008A002357A IT MI20082357 A ITMI20082357 A IT MI20082357A IT 1392501 B1 IT1392501 B1 IT 1392501B1
Authority
IT
Italy
Prior art keywords
order
eco
implementation
basic cell
engineering change
Prior art date
Application number
ITMI2008A002357A
Other languages
English (en)
Inventor
Massimiliano Innocenti
Matteo Pizzotti
Pankaj Rohilla
Lorenzo Cali
Claudio Mucci
Luca Ciccarelli
Valentina Nardone
Original Assignee
St Microelectronics Pvt Ltd
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Pvt Ltd, St Microelectronics Srl filed Critical St Microelectronics Pvt Ltd
Priority to ITMI2008A002357A priority Critical patent/IT1392501B1/it
Priority to US12/648,075 priority patent/US7965107B2/en
Publication of ITMI20082357A1 publication Critical patent/ITMI20082357A1/it
Application granted granted Critical
Publication of IT1392501B1 publication Critical patent/IT1392501B1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
ITMI2008A002357A 2008-12-30 2008-12-30 Cella di base per implementazione di un ordine di modifica o engineering change order (eco) IT1392501B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ITMI2008A002357A IT1392501B1 (it) 2008-12-30 2008-12-30 Cella di base per implementazione di un ordine di modifica o engineering change order (eco)
US12/648,075 US7965107B2 (en) 2008-12-30 2009-12-28 Base cell for engineering change order (ECO) implementation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI2008A002357A IT1392501B1 (it) 2008-12-30 2008-12-30 Cella di base per implementazione di un ordine di modifica o engineering change order (eco)

Publications (2)

Publication Number Publication Date
ITMI20082357A1 ITMI20082357A1 (it) 2010-06-30
IT1392501B1 true IT1392501B1 (it) 2012-03-09

Family

ID=40896364

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI2008A002357A IT1392501B1 (it) 2008-12-30 2008-12-30 Cella di base per implementazione di un ordine di modifica o engineering change order (eco)

Country Status (2)

Country Link
US (1) US7965107B2 (it)
IT (1) IT1392501B1 (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4683833B2 (ja) * 2003-10-31 2011-05-18 株式会社半導体エネルギー研究所 機能回路及びその設計方法
IT1399755B1 (it) * 2010-04-30 2013-05-03 St Microelectronics Srl Cella di base per implementazione di un ordine di modifica o engineering change order (eco) perfezionata.
US8341588B2 (en) * 2010-10-04 2012-12-25 International Business Machines Corporation Semiconductor layer forming method and structure
US8810280B2 (en) 2011-10-06 2014-08-19 Oracle International Corporation Low leakage spare gates for integrated circuits
ITTO20120074A1 (it) 2012-01-30 2013-07-31 St Microelectronics Srl Circuito elettronico traslatore di livello ad accoppiamento capacitivo e di tipo asincrono
US8645892B1 (en) 2013-01-07 2014-02-04 Freescale Semiconductor, Inc. Configurable circuit and mesh structure for integrated circuit
US10146900B2 (en) 2015-09-17 2018-12-04 Qualcomm Incorporated Hybrid diffusion standard library cells, and related systems and methods
KR102419644B1 (ko) 2015-10-26 2022-07-11 삼성전자주식회사 Eco 셀, 그것의 레이아웃 및 eco 셀을 포함하는 집적 회로
US10127340B2 (en) 2016-09-30 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
US10339250B2 (en) 2016-11-29 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method
US11301614B1 (en) * 2019-12-31 2022-04-12 Synopsys, Inc. Feasibility analysis of engineering change orders

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502404A (en) * 1995-04-28 1996-03-26 Texas Instruments Incorporated Gate array cell with predefined connection patterns
US6255845B1 (en) * 1999-11-16 2001-07-03 Advanced Micro Devices, Inc. Efficient use of spare gates for post-silicon debug and enhancements
DE102004007398B4 (de) * 2004-02-16 2007-10-18 Infineon Technologies Ag Konfigurierbare Gate-Array-Zelle mit erweiterter Gate-Elektrode
US7137094B2 (en) * 2004-04-16 2006-11-14 Taiwan Semiconductor Manufacturing Company Method for reducing layers revision in engineering change order
JP2006049780A (ja) * 2004-08-09 2006-02-16 Elpida Memory Inc 半導体集積回路装置
KR100769128B1 (ko) * 2005-12-29 2007-10-22 동부일렉트로닉스 주식회사 Ｅｃｏ셀 그리고, ｅｃｏ셀의 배치 및 루팅방법
JP2008004790A (ja) * 2006-06-23 2008-01-10 Oki Electric Ind Co Ltd スタンダードセル

Also Published As

Publication number Publication date
US7965107B2 (en) 2011-06-21
US20100164547A1 (en) 2010-07-01
ITMI20082357A1 (it) 2010-06-30

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