JP2005322375A - 直列入/出力インターフェースを有するマルチポートメモリ素子 - Google Patents
直列入/出力インターフェースを有するマルチポートメモリ素子 Download PDFInfo
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- JP2005322375A JP2005322375A JP2004195067A JP2004195067A JP2005322375A JP 2005322375 A JP2005322375 A JP 2005322375A JP 2004195067 A JP2004195067 A JP 2004195067A JP 2004195067 A JP2004195067 A JP 2004195067A JP 2005322375 A JP2005322375 A JP 2005322375A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
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Abstract
【解決手段】直列入/出力インターフェースを支援する多数のポートを備えるマルチポートメモリ素子において、メモリコアと、前記多数のポートにパケット形態で入力されたコマンド及びアドレスを用いて内部コマンド信号、内部アドレス信号及び制御信号を生成するための制御手段と、多数のモード選択パッドに印加された信号を組み合わせてテストモードフラグ信号を生成するためのモード選択手段とを備え、前記テストモードフラグ信号に応答して前記送信パッド及び受信パッドに割り当てられた入/出力データは前記ポートを通じて前記メモリコアと交換し、前記送信パッド及び受信パッドに割り当てられたコマンド、アドレス及び制御信号は前記ポート及び前記制御手段でバイパスされて前記メモリコアに提供する。
【選択図】 図8
Description
上記したように、好適な実施例を用いて本発明を説明してきたが、本発明の請求の範囲を逸脱することなく種々の改変が可能であることは当業者には明らかであろう。
TL バス接続部
100 制御部
200 メモリセルアレイ
210 ビット線感知増幅器アレイ
Claims (5)
- 直列入/出力インターフェースを支援する多数のポート(送信パッド及び受信パッドを備える)を備えるマルチポートメモリ素子であって、
メモリコアと、
前記多数のポートにパケット形態で入力されたコマンド及びアドレスを用いて前記コマンドに対応する前記メモリコアの動作に必要な内部コマンド信号、内部アドレス信号及び制御信号を生成するための制御手段と、
多数のモード選択パッドに印加された信号を組み合わせてテストモードフラグ信号を生成するためのモード選択手段とを備え、
前記テストモードフラグ信号に応答して、テストモードで前記送信パッド及び受信パッドに割り当てられた入/出力データは、前記ポートを通じて前記メモリコアと交換し、テストモードで前記送信パッド及び受信パッドに割り当てられたコマンド、アドレス及び制御信号は前記ポート及び前記制御手段からバイパスされて前記メモリコアに提供されるようにする直列入/出力インターフェースを有するマルチポートメモリ素子。 - テストモードで信頼性テストを提供するためのMRSコマンドに割り当てられたエントリー入力パッドと、
前記エントリー入力パッドに印加された前記MRSコマンド及び前記制御手段からバイパスされたアドレスに応答して、前記メモリコアに対する多数のテストモードを提供するためのテストロジックをさらに備えることを特徴とする請求項1に記載の直列入/出力インターフェースを有するマルチポートメモリ素子。 - 前記テストモードフラグ信号に応答して、テストモードで前記制御手段からバイパスされた前記コマンド及びアドレスを合算することにより、バイパス安定性をチェックするための合算ロジックをさらに備えることを特徴とする請求項1に記載の直列入/出力インターフェースを有するマルチポートメモリ素子。
- 前記合算ロジックの出力を外部に引き出すためのウエハーテスト用パッドをさらに備えることを特徴とする請求項3に記載の直列入/出力インターフェースを有するマルチポートメモリ素子。
- 前記制御手段は、
テストモードで前記送信パッド及び受信パッドに割り当てられたコマンド、アドレス及び制御信号をバイパスする過程でバッファリングを行い、該当コマンドに対して同時に使用されない内部コマンド信号、内部アドレス信号及び内部制御信号として前記メモリコアに提供することを特徴とする請求項1〜4のいずれか一項に記載の直列入/出力インターフェースを有するマルチポートメモリ素子。
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KR2004-031980 | 2004-05-06 |
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JP4711646B2 JP4711646B2 (ja) | 2011-06-29 |
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US (1) | US7089465B2 (ja) |
JP (1) | JP4711646B2 (ja) |
KR (1) | KR100609038B1 (ja) |
CN (1) | CN100452240C (ja) |
TW (1) | TWI254943B (ja) |
Cited By (12)
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JP2007095276A (ja) * | 2005-09-29 | 2007-04-12 | Hynix Semiconductor Inc | 直列入/出力インターフェスを有するマルチポートメモリ素子 |
JP2007287306A (ja) * | 2006-04-13 | 2007-11-01 | Hynix Semiconductor Inc | 直列入/出力インターフェースを有するマルチポートメモリ素子及びその動作モードの制御方法 |
JP2007287305A (ja) * | 2006-04-13 | 2007-11-01 | Hynix Semiconductor Inc | 半導体メモリ素子 |
JP2007287307A (ja) * | 2006-04-13 | 2007-11-01 | Hynix Semiconductor Inc | マルチポートメモリ素子 |
JP2008016176A (ja) * | 2006-06-30 | 2008-01-24 | Hynix Semiconductor Inc | 直列入出力インターフェースを有するマルチポートメモリ素子 |
US7596046B2 (en) | 2006-11-15 | 2009-09-29 | Hynix Semiconductor Inc. | Data conversion circuit, and semiconductor memory apparatus using the same |
US7599242B2 (en) | 2005-09-28 | 2009-10-06 | Hynix Semiconductor Inc. | Test circuit for multi-port memory device |
JP2010003377A (ja) * | 2008-06-23 | 2010-01-07 | Elpida Memory Inc | 半導体装置およびデータ処理システム |
US7755959B2 (en) | 2007-06-08 | 2010-07-13 | Hynix Semiconductor Inc. | Semiconductor memory device with reduced number of channels for test operation |
US7855570B2 (en) | 2006-12-27 | 2010-12-21 | Hynix Semiconductor Inc. | Semiconductor device for performing mount test in response to internal test mode signals |
US8213531B2 (en) | 2007-08-10 | 2012-07-03 | SK hynix, Inc. | Apparatus for transmitting signal in semiconductor integrated circuit |
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CN103345438B (zh) * | 2013-05-31 | 2015-02-18 | 中国兵器工业第二○三研究所 | 串行接口故障检测装置及方法 |
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- 2004-05-06 KR KR1020040031980A patent/KR100609038B1/ko active IP Right Grant
- 2004-06-24 TW TW093118305A patent/TWI254943B/zh active
- 2004-06-25 US US10/877,318 patent/US7089465B2/en active Active
- 2004-06-30 JP JP2004195067A patent/JP4711646B2/ja active Active
- 2004-12-01 CN CNB200410096817XA patent/CN100452240C/zh active Active
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Cited By (15)
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US7808851B2 (en) | 2005-09-28 | 2010-10-05 | Hynix Semiconductor Inc. | Test circuit for multi-port memory device |
US7599242B2 (en) | 2005-09-28 | 2009-10-06 | Hynix Semiconductor Inc. | Test circuit for multi-port memory device |
JP2007095276A (ja) * | 2005-09-29 | 2007-04-12 | Hynix Semiconductor Inc | 直列入/出力インターフェスを有するマルチポートメモリ素子 |
JP2007287307A (ja) * | 2006-04-13 | 2007-11-01 | Hynix Semiconductor Inc | マルチポートメモリ素子 |
JP2007287305A (ja) * | 2006-04-13 | 2007-11-01 | Hynix Semiconductor Inc | 半導体メモリ素子 |
JP2007287306A (ja) * | 2006-04-13 | 2007-11-01 | Hynix Semiconductor Inc | 直列入/出力インターフェースを有するマルチポートメモリ素子及びその動作モードの制御方法 |
JP2008016176A (ja) * | 2006-06-30 | 2008-01-24 | Hynix Semiconductor Inc | 直列入出力インターフェースを有するマルチポートメモリ素子 |
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US8031552B2 (en) | 2006-06-30 | 2011-10-04 | Hynix Semiconductor Inc. | Multi-port memory device with serial input/output interface |
US7596046B2 (en) | 2006-11-15 | 2009-09-29 | Hynix Semiconductor Inc. | Data conversion circuit, and semiconductor memory apparatus using the same |
US7855570B2 (en) | 2006-12-27 | 2010-12-21 | Hynix Semiconductor Inc. | Semiconductor device for performing mount test in response to internal test mode signals |
US7755959B2 (en) | 2007-06-08 | 2010-07-13 | Hynix Semiconductor Inc. | Semiconductor memory device with reduced number of channels for test operation |
US8213531B2 (en) | 2007-08-10 | 2012-07-03 | SK hynix, Inc. | Apparatus for transmitting signal in semiconductor integrated circuit |
JP2010003377A (ja) * | 2008-06-23 | 2010-01-07 | Elpida Memory Inc | 半導体装置およびデータ処理システム |
US8829933B2 (en) | 2009-12-28 | 2014-09-09 | SK Hynix Inc. | Semiconductor apparatus and probe test method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN100452240C (zh) | 2009-01-14 |
KR20050106912A (ko) | 2005-11-11 |
TWI254943B (en) | 2006-05-11 |
US7089465B2 (en) | 2006-08-08 |
JP4711646B2 (ja) | 2011-06-29 |
US20050251713A1 (en) | 2005-11-10 |
KR100609038B1 (ko) | 2006-08-09 |
TW200537513A (en) | 2005-11-16 |
CN1694180A (zh) | 2005-11-09 |
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