JP2005294640A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2005294640A JP2005294640A JP2004109243A JP2004109243A JP2005294640A JP 2005294640 A JP2005294640 A JP 2005294640A JP 2004109243 A JP2004109243 A JP 2004109243A JP 2004109243 A JP2004109243 A JP 2004109243A JP 2005294640 A JP2005294640 A JP 2005294640A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
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- 239000000126 substance Substances 0.000 claims description 7
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- 239000002994 raw material Substances 0.000 claims description 4
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- 230000006866 deterioration Effects 0.000 abstract description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 15
- 239000010949 copper Substances 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
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- 235000012239 silicon dioxide Nutrition 0.000 description 9
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- 239000002904 solvent Substances 0.000 description 8
- -1 polymethylsiloxane Polymers 0.000 description 6
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
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- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- HMMGMWAXVFQUOA-UHFFFAOYSA-N octamethylcyclotetrasiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O[Si](C)(C)O1 HMMGMWAXVFQUOA-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】 基板1上に層間絶縁膜3を形成した後、層間絶縁膜上に塗布法により有機系材料からなる絶縁膜5を形成する工程と、有機系材料からなる絶縁膜および層間絶縁膜に電子線を照射して少なくとも有機系材料からなる絶縁膜を焼成する工程と、を備えている。
【選択図】 図1
Description
1)機械的強度(硬度)が2倍程度に向上
2)焼成温度が従来の400℃から300℃程度まで低温化可能であり
3)焼成時間が従来の30分程度から2分程度まで短時間化可能
である。また、レジストプロセスにおけるマスクに適用した場合には、上記に加えて、
4)エッチングマスクとしての耐性(選択比)を2倍程度に向上させることが可能
であった。
本発明の第1実施形態による半導体装置の製造方法を図1乃至図3を参照して説明する。図1乃至図3は、本実施形態による半導体装置の製造方法を示す工程断面図である。
1)機械的強度(硬度)が2倍に向上
2)焼成温度が従来の400℃から300℃まで低温化
3)焼成時間が従来の30分程度から2分程度まで短時間化
4)低誘電率層間絶縁膜の上下の界面における密着強度が3倍に向上
させることが可能であった。
1)機械的強度(硬度)が2倍程度に向上、
するという効果が確認できた。
2)エッチングマスクとしての耐性(選択比)が2倍程度に向上した。
次に、本発明の第2実施形態による半導体装置の製造方法を図7(a)乃至図7(c)を参照して説明する。図7(a)乃至図7(c)は、本実施形態による半導体装置の製造方法の製造工程を示す断面図である。本実施形態の製造方法は、図7(a)乃至図7(c)に示すようにダマシン法により配線を作成する際に用いられる。
次に、本発明の第3実施形態による半導体装置の製造方法を図8(a)乃至図8(c)を参照して説明する。図8(a)乃至図8(c)は、本実施形態による半導体装置の製造方法の製造工程を示す断面図である。本実施形態による製造方法は、図8(a)乃至図8(c)に示すようにデュアルダマシン法により配線を形成する際に用いたものである。
3 低誘電率層間絶縁膜
5 有機樹脂
Claims (5)
- 基板上に層間絶縁膜を形成した後、前記層間絶縁膜上に塗布法により有機系材料からなる絶縁膜を形成する工程と、
前記有機系材料からなる絶縁膜および前記層間絶縁膜に電子線を照射して少なくとも前記有機系材料からなる絶縁膜を焼成する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記有機系材料からなる絶縁膜を形成する工程は、
前記有機系材料からなる絶縁膜を構成する物質の前駆体もしくは前記物質を含む絶縁膜原料を前記層間絶縁膜上に塗布する工程と、
300℃以下の温度で多くとも2分間の熱処理を少なくとも一回行う工程と
を備えたことを特徴とする請求項1記載の半導体装置の製造方法。 - 前記層間絶縁膜は低誘電率絶縁膜であり、前記電子線の照射によって前記層間絶縁膜を構成する低誘電率絶縁膜も焼成されることを特徴とする請求項1または2記載の半導体装置の製造方法。
- 基板上に低誘電率絶縁膜を形成する工程と、
前記低誘電率絶縁膜上に絶縁体からなる犠牲膜を形成する工程と、
前記犠牲膜を介して前記低誘電率絶縁膜に電子線を照射する工程と、
前記犠牲膜を除去する工程と
を備えたことを特徴とする半導体装置の製造方法。 - 前記低誘電率絶縁膜は、2層以上を積層して形成されることを特徴とする請求項3または4記載の半導体装置の製造方法。
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JP2006190962A (ja) * | 2004-12-09 | 2006-07-20 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2007036067A (ja) * | 2005-07-28 | 2007-02-08 | Sony Corp | 半導体装置の製造方法 |
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JP4357434B2 (ja) * | 2005-02-25 | 2009-11-04 | 株式会社東芝 | 半導体装置の製造方法 |
JP2007059617A (ja) * | 2005-08-24 | 2007-03-08 | Toshiba Corp | 半導体装置の製造方法 |
US7514354B2 (en) * | 2005-12-30 | 2009-04-07 | Samsung Electronics Co., Ltd | Methods for forming damascene wiring structures having line and plug conductors formed from different materials |
JP5142538B2 (ja) * | 2007-01-26 | 2013-02-13 | 株式会社東芝 | 半導体装置の製造方法 |
US9397004B2 (en) * | 2014-01-27 | 2016-07-19 | GlobalFoundries, Inc. | Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings |
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US6153525A (en) * | 1997-03-13 | 2000-11-28 | Alliedsignal Inc. | Methods for chemical mechanical polish of organic polymer dielectric films |
JP2001345380A (ja) | 2000-05-31 | 2001-12-14 | Toshiba Corp | 半導体装置の製造方法および半導体装置 |
US6746969B2 (en) * | 2000-10-20 | 2004-06-08 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JP3813877B2 (ja) | 2001-01-19 | 2006-08-23 | 東京エレクトロン株式会社 | 基板の処理方法 |
US6890703B2 (en) * | 2002-03-06 | 2005-05-10 | International Business Machines Corporation | Preparation of crosslinked particles from polymers having activatible crosslinking groups |
JP2003289099A (ja) | 2002-03-27 | 2003-10-10 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP3692109B2 (ja) * | 2002-10-24 | 2005-09-07 | 株式会社東芝 | 半導体装置の製造方法 |
JP3668222B2 (ja) * | 2002-11-07 | 2005-07-06 | 株式会社東芝 | 半導体装置の製造方法 |
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JP2006190962A (ja) * | 2004-12-09 | 2006-07-20 | Fujitsu Ltd | 半導体装置の製造方法 |
JP4667165B2 (ja) * | 2004-12-09 | 2011-04-06 | 富士通株式会社 | 半導体装置の製造方法 |
JP2007036067A (ja) * | 2005-07-28 | 2007-02-08 | Sony Corp | 半導体装置の製造方法 |
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