JP4357434B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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Description
先ず、本発明に係る第1実施形態を図1〜図4を参照しつつ詳しく説明する。図1〜図3は、それぞれ本実施形態に係る半導体装置の製造方法を示す工程断面図である。また、図4は、本実施形態に係る半導体装置の製造装置を簡略化して示す断面図である。
この化学反応式(1)において、≡Si−CH3 はSiCO:H膜106中に含まれるメチル基である。また、この化学反応により生成された ≡Si−OH基は、水分(H2O)を吸着するいわゆる吸湿サイトとして働く。この≡Si−OH基により、下層膜のSiCO:H膜106と上層膜のSiO2 膜107との界面であるSiCO:H膜106の表層部に、図9に示すように、水分(H2O)が吸着した脆弱な層106aが形成される。この脆弱層106aは、SiCO:H膜106の他の部分に比べて脆く、機械的強度(物理的強度)が低い。すなわち、脆弱層106aは、SiCO:H膜106の他の部分に比べて、外力によるストレスに対する耐久性が低い。このため、SiO2 膜107形成工程の後工程であるCMP工程においてSiCO:H膜106とSiO2 膜107との界面である脆弱層106aにストレスが掛かると、図9に示すように、脆弱層106aとSiO2 膜107との間に膜剥がれが容易に生じてしまう。
次に、本発明に係る第2実施形態を図5を参照しつつ説明する。図5は、本実施形態に係る半導体装置の製造方法を示す工程断面図である。なお、第1実施形態と同一部分には同一符号を付して、その詳しい説明を省略する。
次に、本発明に係る第3実施形態を図6〜図8を参照しつつ説明する。図6〜図8は、それぞれ本実施形態に係る半導体装置の製造方法を示す工程断面図である。なお、第1および第2の各実施形態と同一部分には同一符号を付して、その詳しい説明を省略する。
続けて、下層SiCO:H膜6の表層部と雰囲気中の水分(H2O)とがさらに反応して、次の化学反応式(3)により表される化学反応が起きる。
化学反応式(2)において、≡Si−CH3 は下層SiCO:H膜6中に含まれるメチル基である。化学反応式(3)により表される化学反応により生成された水酸基(≡Si−OH)は、水分(H2O)を吸着するいわゆる吸湿サイトとして働く。このため、上層配線用凹部45を形成する際にNH3 ガスをエッチングガスとして用いると、下層SiCO:H膜6の表面に水分が付着し易い。水分が付着した上層配線用凹部45内にCu上層配線15を形成すると、Cu上層配線15が容易に酸化(腐蝕)されて劣化する。この結果、配線の信頼性や性能が容易に低下する。
Claims (1)
- 少なくとも酸素を含むとともに比誘電率が3.3以下であり、かつ、導電体が埋め込まれる低比誘電率膜を基板上に設け、
前記低比誘電率膜を成膜した処理室とは別の処理室であって内部が酸素以外の元素から構成される材料により覆われているとともに実質的に酸素フリーの雰囲気下に設定された処理室内に、前記低比誘電率膜が設けられた前記基板を収容した後、希ガスを主成分とするガスの放電によるプラズマ処理を前記低比誘電率膜に施し、
酸素を含む材料および酸素と反応する元素を含む材料の少なくとも一方の材料からなるとともに導電体が埋め込まれる第1の絶縁膜を、プラズマCVD法により前記低比誘電率膜上に設ける、
半導体装置の製造方法であって、
前記第1の絶縁膜を設けるのに先立って、酸素以外の元素から構成されるとともに導電体が埋め込まれる第2の絶縁膜を、前記処理室内で前記低比誘電率膜に前記プラズマ処理を施しつつ、前記プラズマ処理により前記処理室の内部を覆っている酸素以外の元素から構成される材料自体を前記低比誘電率膜の表面に堆積させることで前記低比誘電率膜上に設けるとともに、前記低比誘電率膜が設けられた前記基板を前記第2の絶縁膜の成膜が終了するまで酸素と非接触の雰囲気下に保持する
ことを特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005050939A JP4357434B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置の製造方法 |
TW095106349A TWI309443B (en) | 2005-02-25 | 2006-02-24 | Method of manufacturing semiconductor device |
US11/360,703 US20060199373A1 (en) | 2005-02-25 | 2006-02-24 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2005050939A JP4357434B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置の製造方法 |
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US7897495B2 (en) * | 2006-12-12 | 2011-03-01 | Applied Materials, Inc. | Formation of epitaxial layer containing silicon and carbon |
JP5142538B2 (ja) * | 2007-01-26 | 2013-02-13 | 株式会社東芝 | 半導体装置の製造方法 |
JP5424551B2 (ja) * | 2007-11-07 | 2014-02-26 | ローム株式会社 | 半導体装置 |
JP2009283812A (ja) * | 2008-05-26 | 2009-12-03 | Renesas Technology Corp | 半導体装置の製造方法 |
US8334204B2 (en) * | 2008-07-24 | 2012-12-18 | Tokyo Electron Limited | Semiconductor device and manufacturing method therefor |
US20100109155A1 (en) * | 2008-11-05 | 2010-05-06 | Chartered Semiconductor Manufacturing, Ltd. | Reliable interconnect integration |
JP5238615B2 (ja) * | 2009-06-04 | 2013-07-17 | 株式会社東芝 | 半導体装置の製造方法 |
SG191213A1 (en) * | 2010-12-28 | 2013-07-31 | Kirin Brewery | Gas-barrier plastic molded product and manufacturing process therefor |
US9812380B2 (en) * | 2014-05-22 | 2017-11-07 | Microchip Technology Incorporated | Bumps bonds formed as metal line interconnects in a semiconductor device |
US9754822B1 (en) | 2016-03-02 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
US10199500B2 (en) | 2016-08-02 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer film device and method |
CN113690174A (zh) * | 2020-05-19 | 2021-11-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US20230187395A1 (en) * | 2021-12-10 | 2023-06-15 | Intel Corporation | Oxide and carbon layers at a surface of a substrate for hybrid bonding |
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FI119941B (fi) * | 1999-10-15 | 2009-05-15 | Asm Int | Menetelmä nanolaminaattien valmistamiseksi |
US6635583B2 (en) * | 1998-10-01 | 2003-10-21 | Applied Materials, Inc. | Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating |
KR100695299B1 (ko) * | 2000-05-12 | 2007-03-14 | 삼성전자주식회사 | 액정 표시 장치용 박막 트랜지스터 기판 및 그의 제조 방법 |
US20070158178A1 (en) * | 2002-07-23 | 2007-07-12 | Tosoh Smd, Inc. | Method and apparatus for deposition of low-k dielectric materials |
JP4068072B2 (ja) * | 2003-01-29 | 2008-03-26 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
DE10319136B4 (de) * | 2003-04-28 | 2008-06-12 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Metallisierungsschicht mit einer mit Stickstoff angereicherten Barrierenschicht mit kleinem ε |
US7141485B2 (en) * | 2003-06-13 | 2006-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits |
US7199046B2 (en) * | 2003-11-14 | 2007-04-03 | Tokyo Electron Ltd. | Structure comprising tunable anti-reflective coating and method of forming thereof |
US20050221020A1 (en) * | 2004-03-30 | 2005-10-06 | Tokyo Electron Limited | Method of improving the wafer to wafer uniformity and defectivity of a deposited dielectric film |
JP4257252B2 (ja) * | 2004-04-01 | 2009-04-22 | 株式会社東芝 | 半導体装置の製造方法 |
US7253123B2 (en) * | 2005-01-10 | 2007-08-07 | Applied Materials, Inc. | Method for producing gate stack sidewall spacers |
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US20060199373A1 (en) | 2006-09-07 |
JP2006237349A (ja) | 2006-09-07 |
TW200634927A (en) | 2006-10-01 |
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