JP2006237349A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2006237349A JP2006237349A JP2005050939A JP2005050939A JP2006237349A JP 2006237349 A JP2006237349 A JP 2006237349A JP 2005050939 A JP2005050939 A JP 2005050939A JP 2005050939 A JP2005050939 A JP 2005050939A JP 2006237349 A JP2006237349 A JP 2006237349A
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- film
- sico
- dielectric constant
- sicn
- relative dielectric
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Abstract
【解決手段】少なくとも酸素を含むとともに比誘電率が3.3以下であり、かつ、Cu膜14が埋め込まれるSiCO:H膜6を半導体基板1上に設ける。続けて、実質的に酸素フリーの雰囲気下に設定された処理室20内にSiCO:H膜6が設けられた半導体基板1を収容した後、Arガスの放電によるプラズマ処理をSiCO:H膜6に施しつつ、酸素と反応する元素を含む材料からなるSiCN:H膜7を設けるとともに、Cu膜14が埋め込まれるSiO2 膜をプラズマCVD法によりSiCN:H膜7上に設ける。
【選択図】図3
Description
先ず、本発明に係る第1実施形態を図1〜図4を参照しつつ詳しく説明する。図1〜図3は、それぞれ本実施形態に係る半導体装置の製造方法を示す工程断面図である。また、図4は、本実施形態に係る半導体装置の製造装置を簡略化して示す断面図である。
この化学反応式(1)において、≡Si−CH3 はSiCO:H膜106中に含まれるメチル基である。また、この化学反応により生成された ≡Si−OH基は、水分(H2O)を吸着するいわゆる吸湿サイトとして働く。この≡Si−OH基により、下層膜のSiCO:H膜106と上層膜のSiO2 膜107との界面であるSiCO:H膜106の表層部に、図9に示すように、水分(H2O)が吸着した脆弱な層106aが形成される。この脆弱層106aは、SiCO:H膜106の他の部分に比べて脆く、機械的強度(物理的強度)が低い。すなわち、脆弱層106aは、SiCO:H膜106の他の部分に比べて、外力によるストレスに対する耐久性が低い。このため、SiO2 膜107形成工程の後工程であるCMP工程においてSiCO:H膜106とSiO2 膜107との界面である脆弱層106aにストレスが掛かると、図9に示すように、脆弱層106aとSiO2 膜107との間に膜剥がれが容易に生じてしまう。
次に、本発明に係る第2実施形態を図5を参照しつつ説明する。図5は、本実施形態に係る半導体装置の製造方法を示す工程断面図である。なお、第1実施形態と同一部分には同一符号を付して、その詳しい説明を省略する。
次に、本発明に係る第3実施形態を図6〜図8を参照しつつ説明する。図6〜図8は、それぞれ本実施形態に係る半導体装置の製造方法を示す工程断面図である。なお、第1および第2の各実施形態と同一部分には同一符号を付して、その詳しい説明を省略する。
続けて、下層SiCO:H膜6の表層部と雰囲気中の水分(H2O)とがさらに反応して、次の化学反応式(3)により表される化学反応が起きる。
化学反応式(2)において、≡Si−CH3 は下層SiCO:H膜6中に含まれるメチル基である。化学反応式(3)により表される化学反応により生成された水酸基(≡Si−OH)は、水分(H2O)を吸着するいわゆる吸湿サイトとして働く。このため、上層配線用凹部45を形成する際にNH3 ガスをエッチングガスとして用いると、下層SiCO:H膜6の表面に水分が付着し易い。水分が付着した上層配線用凹部45内にCu上層配線15を形成すると、Cu上層配線15が容易に酸化(腐蝕)されて劣化する。この結果、配線の信頼性や性能が容易に低下する。
Claims (5)
- 少なくとも酸素を含むとともに比誘電率が3.3以下であり、かつ、導電体が埋め込まれる低比誘電率膜を基板上に設け、
内部が酸素以外の元素から構成される材料により覆われているとともに実質的に酸素フリーの雰囲気下に設定された処理室内に、前記低比誘電率膜が設けられた前記基板を収容した後、希ガスを主成分とするガスの放電によるプラズマ処理を前記低比誘電率膜に施し、
酸素を含む材料および酸素と反応する元素を含む材料の少なくとも一方の材料からなるとともに導電体が埋め込まれる第1の絶縁膜を、プラズマCVD法により前記低比誘電率膜上に設ける、
ことを特徴とする半導体装置の製造方法。 - 前記第1の絶縁膜を設けるのに先立って、酸素以外の元素から構成されるとともに導電体が埋め込まれる第2の絶縁膜を、前記処理室内で前記低比誘電率膜に前記プラズマ処理を施しつつ前記低比誘電率膜上に設けるとともに、前記低比誘電率膜が設けられた前記基板を前記第2の絶縁膜の成膜が終了するまで酸素と非接触の雰囲気下に保持することを特徴とする請求項1に記載の半導体装置の製造方法。
- 少なくとも酸素を含むとともに比誘電率が3.3以下であり、かつ、導電体が埋め込まれる第1の低比誘電率膜を基板上に設け、
少なくとも酸素を含むとともに比誘電率が3.3以下であり、かつ、前記第1の低比誘電率膜よりも膜密度が高く、さらに導電体が埋め込まれる第2の低比誘電率膜を前記第1の低比誘電率膜上に設け、
少なくとも前記第1および第2の各低比誘電率膜に電子線を照射する、
ことを特徴とする半導体装置の製造方法。 - 前記第1および第2の各低比誘電率膜に前記電子線を照射した後、酸素を含む材料および酸素と反応する元素を含む材料の少なくとも一方の材料からなるとともに導電体が埋め込まれる第1の絶縁膜を、プラズマCVD法により前記第2の低比誘電率膜上に設けることを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第1および第2の各低比誘電率膜に前記電子線を照射するのに先立って、さらに比誘電率が3.3以下である第3の低比誘電率膜を塗布法により前記第2の低比誘電率膜上に設けた後、前記第1、第2、および第3の各低比誘電率膜に前記電子線を照射することを特徴とする請求項3に記載の半導体装置の製造方法。
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Cited By (8)
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JP2008186849A (ja) * | 2007-01-26 | 2008-08-14 | Toshiba Corp | 半導体装置の製造方法 |
JP2009117652A (ja) * | 2007-11-07 | 2009-05-28 | Rohm Co Ltd | 半導体装置 |
JP2009283812A (ja) * | 2008-05-26 | 2009-12-03 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2010034517A (ja) * | 2008-07-24 | 2010-02-12 | Tokyo Electron Ltd | 半導体装置および半導体装置の製造方法 |
JP2010283136A (ja) * | 2009-06-04 | 2010-12-16 | Toshiba Corp | 半導体装置の製造方法 |
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KR100695299B1 (ko) * | 2000-05-12 | 2007-03-14 | 삼성전자주식회사 | 액정 표시 장치용 박막 트랜지스터 기판 및 그의 제조 방법 |
US20070158178A1 (en) * | 2002-07-23 | 2007-07-12 | Tosoh Smd, Inc. | Method and apparatus for deposition of low-k dielectric materials |
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US20050221020A1 (en) * | 2004-03-30 | 2005-10-06 | Tokyo Electron Limited | Method of improving the wafer to wafer uniformity and defectivity of a deposited dielectric film |
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JP2010034517A (ja) * | 2008-07-24 | 2010-02-12 | Tokyo Electron Ltd | 半導体装置および半導体装置の製造方法 |
JP2010283136A (ja) * | 2009-06-04 | 2010-12-16 | Toshiba Corp | 半導体装置の製造方法 |
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