US20150132946A1 - Methods for barrier interface preparation of copper interconnect - Google Patents
Methods for barrier interface preparation of copper interconnect Download PDFInfo
- Publication number
- US20150132946A1 US20150132946A1 US14/558,548 US201414558548A US2015132946A1 US 20150132946 A1 US20150132946 A1 US 20150132946A1 US 201414558548 A US201414558548 A US 201414558548A US 2015132946 A1 US2015132946 A1 US 2015132946A1
- Authority
- US
- United States
- Prior art keywords
- layer
- barrier layer
- copper
- metallic barrier
- integrated system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 165
- 230000004888 barrier function Effects 0.000 title claims abstract description 163
- 239000010949 copper Substances 0.000 title claims abstract description 154
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 151
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 149
- 238000002360 preparation method Methods 0.000 title description 6
- 230000008569 process Effects 0.000 claims abstract description 124
- 238000000151 deposition Methods 0.000 claims abstract description 75
- 238000007306 functionalization reaction Methods 0.000 claims abstract description 46
- 230000000536 complexating effect Effects 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000000203 mixture Substances 0.000 claims abstract description 9
- 238000001035 drying Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 85
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 230000008021 deposition Effects 0.000 claims description 44
- 238000004140 cleaning Methods 0.000 claims description 21
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical group [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 20
- 238000000231 atomic layer deposition Methods 0.000 claims description 19
- 229910044991 metal oxide Inorganic materials 0.000 claims description 14
- 150000004706 metal oxides Chemical class 0.000 claims description 14
- 238000005240 physical vapour deposition Methods 0.000 claims description 14
- 229910052715 tantalum Inorganic materials 0.000 claims description 12
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 229910052707 ruthenium Inorganic materials 0.000 claims description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- RMVRSNDYEFQCLF-UHFFFAOYSA-N thiophenol Chemical compound SC1=CC=CC=C1 RMVRSNDYEFQCLF-UHFFFAOYSA-N 0.000 claims description 6
- KBPLFHHGFOOTCA-UHFFFAOYSA-N 1-Octanol Chemical compound CCCCCCCCO KBPLFHHGFOOTCA-UHFFFAOYSA-N 0.000 claims description 4
- GUUVPOWQJOLRAS-UHFFFAOYSA-N Diphenyl disulfide Chemical compound C=1C=CC=CC=1SSC1=CC=CC=C1 GUUVPOWQJOLRAS-UHFFFAOYSA-N 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 239000010955 niobium Substances 0.000 claims description 4
- 150000003573 thiols Chemical class 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 3
- 150000007513 acids Chemical class 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- CHEANNSDVJOIBS-MHZLTWQESA-N (3s)-3-cyclopropyl-3-[3-[[3-(5,5-dimethylcyclopenten-1-yl)-4-(2-fluoro-5-methoxyphenyl)phenyl]methoxy]phenyl]propanoic acid Chemical compound COC1=CC=C(F)C(C=2C(=CC(COC=3C=C(C=CC=3)[C@@H](CC(O)=O)C3CC3)=CC=2)C=2C(CCC=2)(C)C)=C1 CHEANNSDVJOIBS-MHZLTWQESA-N 0.000 claims description 2
- GEZGAZKEOUKLBR-UHFFFAOYSA-N 1-phenylpyrrole Chemical compound C1=CC=CN1C1=CC=CC=C1 GEZGAZKEOUKLBR-UHFFFAOYSA-N 0.000 claims description 2
- REHRCHHNCOTPBV-UHFFFAOYSA-N 2,5-dithiophen-2-yl-1h-pyrrole Chemical compound C1=CSC(C=2NC(=CC=2)C=2SC=CC=2)=C1 REHRCHHNCOTPBV-UHFFFAOYSA-N 0.000 claims description 2
- XQEHNEWIRZWJPI-UHFFFAOYSA-N 22-sulfanyldocosanoic acid Chemical compound OC(=O)CCCCCCCCCCCCCCCCCCCCCS XQEHNEWIRZWJPI-UHFFFAOYSA-N 0.000 claims description 2
- FTGKPHQQHPCLAI-UHFFFAOYSA-N 3,6-dithiatetracyclo[6.4.0.02,4.05,7]dodeca-1(12),8,10-triene Chemical compound C12=CC=CC=C2C2SC2C2C1S2 FTGKPHQQHPCLAI-UHFFFAOYSA-N 0.000 claims description 2
- URDOJQUSEUXVRP-UHFFFAOYSA-N 3-triethoxysilylpropyl 2-methylprop-2-enoate Chemical compound CCO[Si](OCC)(OCC)CCCOC(=O)C(C)=C URDOJQUSEUXVRP-UHFFFAOYSA-N 0.000 claims description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- BWGNESOTFCXPMA-UHFFFAOYSA-N Dihydrogen disulfide Chemical compound SS BWGNESOTFCXPMA-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 235000021355 Stearic acid Nutrition 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 125000003118 aryl group Chemical group 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- VTXVGVNLYGSIAR-UHFFFAOYSA-N decane-1-thiol Chemical compound CCCCCCCCCCS VTXVGVNLYGSIAR-UHFFFAOYSA-N 0.000 claims description 2
- JMLPVHXESHXUSV-UHFFFAOYSA-N dodecane-1,1-diamine Chemical compound CCCCCCCCCCCC(N)N JMLPVHXESHXUSV-UHFFFAOYSA-N 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 2
- QJAOYSPHSNGHNC-UHFFFAOYSA-N octadecane-1-thiol Chemical compound CCCCCCCCCCCCCCCCCCS QJAOYSPHSNGHNC-UHFFFAOYSA-N 0.000 claims description 2
- QIQXTHQIDYTFRH-UHFFFAOYSA-N octadecanoic acid Chemical compound CCCCCCCCCCCCCCCCCC(O)=O QIQXTHQIDYTFRH-UHFFFAOYSA-N 0.000 claims description 2
- OQCDKBAXFALNLD-UHFFFAOYSA-N octadecanoic acid Natural products CCCCCCCC(C)CCCCCCCCC(O)=O OQCDKBAXFALNLD-UHFFFAOYSA-N 0.000 claims description 2
- YAYGSLOSTXKUBW-UHFFFAOYSA-N ruthenium(2+) Chemical compound [Ru+2] YAYGSLOSTXKUBW-UHFFFAOYSA-N 0.000 claims description 2
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 claims description 2
- YNHJECZULSZAQK-UHFFFAOYSA-N tetraphenylporphyrin Chemical class C1=CC(C(=C2C=CC(N2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3N2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 YNHJECZULSZAQK-UHFFFAOYSA-N 0.000 claims description 2
- DUYAAUVXQSMXQP-UHFFFAOYSA-M thioacetate Chemical compound CC([S-])=O DUYAAUVXQSMXQP-UHFFFAOYSA-M 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- YUYCVXFAYWRXLS-UHFFFAOYSA-N trimethoxysilane Chemical compound CO[SiH](OC)OC YUYCVXFAYWRXLS-UHFFFAOYSA-N 0.000 claims description 2
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 202
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 23
- 239000001301 oxygen Substances 0.000 description 23
- 229910052760 oxygen Inorganic materials 0.000 description 23
- 239000010408 film Substances 0.000 description 13
- 238000005137 deposition process Methods 0.000 description 12
- 239000000126 substance Substances 0.000 description 11
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 8
- 239000011261 inert gas Substances 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 239000002094 self assembled monolayer Substances 0.000 description 6
- 239000013545 self-assembled monolayer Substances 0.000 description 6
- 239000002356 single layer Substances 0.000 description 6
- 229910001936 tantalum oxide Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 150000007524 organic acids Chemical class 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- KAESVJOAVNADME-UHFFFAOYSA-N Pyrrole Chemical compound C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000003197 catalytic effect Effects 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 150000001412 amines Chemical class 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 2
- OKIZCWYLBDKLSU-UHFFFAOYSA-M N,N,N-Trimethylmethanaminium chloride Chemical compound [Cl-].C[N+](C)(C)C OKIZCWYLBDKLSU-UHFFFAOYSA-M 0.000 description 2
- 229910003070 TaOx Inorganic materials 0.000 description 2
- 238000007792 addition Methods 0.000 description 2
- 150000001298 alcohols Chemical class 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 2
- 235000005985 organic acids Nutrition 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- 150000004756 silanes Chemical class 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 description 2
- 238000003631 wet chemical etching Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 244000132059 Carica parviflora Species 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- RPNUMPOLZDHAAY-UHFFFAOYSA-N Diethylenetriamine Chemical compound NCCNCCN RPNUMPOLZDHAAY-UHFFFAOYSA-N 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 239000002841 Lewis acid Substances 0.000 description 1
- 239000002879 Lewis base Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000003125 aqueous solvent Substances 0.000 description 1
- -1 citric acid Chemical class 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 125000000524 functional group Chemical group 0.000 description 1
- 150000007517 lewis acids Chemical class 0.000 description 1
- 150000007527 lewis bases Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000007522 mineralic acids Chemical class 0.000 description 1
- 230000008450 motivation Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000007530 organic bases Chemical class 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004375 physisorption Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67196—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the transfer chamber
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45544—Atomic layer deposition [ALD] characterized by the apparatus
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1619—Apparatus for electroless plating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1619—Apparatus for electroless plating
- C23C18/1632—Features specific for the apparatus, e.g. layout of cells and of its equipment, multiple cells
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
- C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/38—Coating with copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67201—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the load-lock chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
- H01L21/6723—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one plating chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Definitions
- Interconnect metallization for vias and trenches may include aluminum alloys and copper.
- Interconnect metallization for vias and trenches may include aluminum alloys and copper.
- the embodiments fill the need enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect with good electro-migration performance and with reduced risk of stress-induce voiding of copper interconnect. Electromigration and stress-induced voiding are affected by the adhesion between the barrier layer and the copper layer, which can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition.
- a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect. The functionalization layer forms strong bonds with barrier layer and with copper to improve adhesion property between the two layers.
- the functionalization layer can also merely enable the deposition of copper over the barrier layer and be replaced by the copper layer. It should be appreciated that the present invention can be implemented in numerous ways, including as a solution, a method, a process, an apparatus, or a system. Several inventive embodiments of the present invention are described below.
- a method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide.
- the method also includes depositing the functionalization layer over the metallic layer in the integrated system.
- the method further includes depositing the copper layer in the copper interconnect structure in the integrated system after the functionalization layer is deposited over the metallic barrier layer.
- an integrated system for processing a substrate in controlled environment to enable deposition of a functionalization layer over a metallic barrier layer of a copper interconnect to improve electromigration performance of the copper interconnect includes a lab-ambient transfer chamber capable of transferring the substrate from a substrate cassette coupled to the lab-ambient transfer chamber into the integrated system.
- the system also includes a vacuum transfer chamber operated under vacuum at a pressure less than 1 Torr.
- the method further includes a vacuum process module for depositing the metallic barrier layer, wherein the vacuum process module for depositing the metallic barrier layer is coupled to the vacuum transfer chamber, and is operated under vacuum at a pressure less than 1 Torr.
- the method includes a controlled-ambient transfer chamber filled with an inert gas selected from a group of inert gases, and a deposition process module used to deposit the functionalization layer on the surface of the metallic barrier layer, wherein the deposition process module used to deposit the functionalization layer is coupled to the controlled-ambient transfer chamber.
- FIGS. 1A-1D show cross sections of a dual-damascene interconnect structure at various stages of interconnect processing.
- FIGS. 2A-2C show cross sections of a metal line structure at various stages of interconnect processing.
- FIG. 3A shows an exemplary process flow of interconnect processing.
- FIG. 3B shows an exemplary integrated system used to process a substrate using a process flow of FIG. 3A .
- FIGS. 4A-4D show cross sections of a metal line structure at various stages of interconnect processing to incorporate a functionalization layer.
- FIGS. 5A-5E show cross sections of an interconnect structure at various stages of interconnect processing to incorporate a functionalization layer.
- FIG. 6A shows an exemplary process flow of interconnect processing that incorporates a functionalization layer.
- FIG. 6B shows an exemplary integrated system used to process a substrate using a process flow of FIG. 6A .
- FIG. 1A shows an exemplary cross-section of an interconnect structure(s) after being patterned by using a dual damascene process sequence.
- the interconnect structure(s) is on a substrate 50 and has a dielectric layer 100 , which was previously fabricated to form a metallization line 101 therein.
- the metallization line is typically fabricated by etching a trench into the dielectric 100 and then filling the trench with a conductive material, such as copper.
- barrier layer 120 used to prevent the copper material 122 , from diffusing into the dielectric 100 .
- the barrier layer 120 can be made of physical vapor deposition (PVD) tantalum nitride (TaN), PVD tantalum (Ta), atomic layer deposition (ALD) TaN, or a combination of these films. Other barrier layer materials can also be used.
- PVD physical vapor deposition
- TaN tantalum nitride
- Ta PVD tantalum
- ALD atomic layer deposition
- a barrier layer 102 is deposited over the planarized copper material 122 to protect the copper material 122 from premature oxidation when via holes 114 are etched through overlying dielectric materials 104 , 106 to the barrier layer 102 .
- the barrier layer 102 is also configured to function as a selective etch stop.
- Exemplary barrier layer 102 materials include silicon nitride (SiN) or silicon carbide (SiC).
- a via dielectric layer 104 is deposited over the barrier layer 102 .
- the via dielectric layer 104 can be made of an organo-silicate glass (OS G, carbon-doped silicon oxide) or other types of dielectric materials, preferably with low dielectric constants.
- Exemplary silicon dioxides can include, a PECVD un-doped TEOS silicon dioxide, a PECVD fluorinated silica glass (FSG), a HDP FSG, OSG, porous OSG, etc. and the like.
- Commercially available dielectric materials including Black Diamond (I) and Black Diamond (II) by Applied Materials of Santa Clara, Calif., Coral by Novellus Systems of San Jose, Aurora by ASM America Inc. of Phoenix, Ariz., can also be used.
- the trench dielectric layer 106 may be a low K dielectric material, such as a carbon-doped oxide (C-oxide).
- the dielectric constant of the low K dielectric material can be about 3.0 or lower.
- both the via and trench dielectric layers are made of the same material, and deposited at the same time to form a continuous film. After the trench dielectric layer 106 is deposited, the substrate 50 that holds the structure(s) undergoes patterning and etching processes to form the vias holes 114 and trenches 116 by known art.
- FIG. 1B shows that after the formation of vias holes 114 and trenches 116 , a barrier layer 130 and a copper layer 132 are deposited to line and fill the via holes 114 and the trenches 116 .
- the barrier layer 130 can be made of tantalum nitride (TaN), tantalum (Ta), Ruthenium (Ru), or a hybrid combination of these materials. While these are the commonly considered materials, other barrier layer materials can also be used.
- Barrier layer materials may be other refractory metal compound including but not limited to titanium (Ti), tungsten (W), zirconium (Zr), hafnium (Hf), molybdenum (Mo), niobium (Nb), vanadium (V), ruthenium (Ru) and chromium (Cr), among others.
- a copper film 132 is then deposited to fill the via holes 114 and the trenches 116 , as shown in FIG. 1C .
- the copper film 132 includes a thin copper seed layer 131 underneath.
- the thickness of the thin copper seed layer is between about 5 angstroms to about 300 angstroms.
- Barrier layer such as Ta, TaN or Ru, if exposed to air for extended period of time, can form Ta x O y (Tantalum oxide), TaO x N y (Tantalum oxynitride), or RuO 2 (Ruthenium oxide).
- Electroless deposition of a metal layer on a substrate is highly dependent upon the surface characteristics and composition of the substrate. Electroless plating of copper on a Ta, TaN, or Ru surface is of interest for both seed layer formation prior to electroplating, and selective deposition of Cu lines within lithographically defined pattern(s). One concern is the inhibition of the electroless deposition process by atomically thin native metal oxide layer formed in the presence of oxygen (O 2 ).
- barrier oxide layer such as tantalum oxide, tantalum oxynitride, or ruthenium oxide
- pure barrier metal or barrier-layer-rich film such as Ta, Ru, or Ta-rich TaN film.
- Ta and/or TaN barrier layers are only used as examples. The description and concept apply to other types of barrier metals, such as Ta or TaN capped with a thin layer of Ru. As described above, poor adhesion can negatively affect the EM performance.
- the formation tantalum oxide or tantalum oxynitride on the barrier layer surface can increase the resistivity of the barrier layer. Due to these issues, it is desirable to use the integrated system to prepare the barrier/copper interface to ensure good adhesion between the barrier layer and copper and to ensure low resistivity of the barrier layer.
- FIG. 1B shows that the barrier layer 130 is a single layer deposited either by ALD or PVD.
- the barrier layer 130 can be deposited by an ALD process to deposit a first barrier layer 130 I , such as TaN, which is followed by a PVD second barrier layer 130 II , such as Ta, as shown in FIG. 1D .
- FIG. 2A shows an exemplary cross-section of a metal line structure after being patterned by a dielectric etch and being removed of photoresist.
- the metal line structure(s) is on a substrate 200 and has a silicon layer 110 , which was previously fabricated to form a gate structure 105 with a gate oxide 121 , spacers 107 and a contact 125 therein.
- the contact 125 is typically fabricated by etching a contact hole into the oxide 103 and then filling the contact hole with a conductive material, such as tungsten.
- Alternative materials may include copper, aluminum or other conductive materials.
- the barrier layer 102 is configured to function as a selective trench etch stop.
- the barrier layer 102 can be made of materials such as silicon nitride (SiN) or silicon carbide (SiC).
- a metal line dielectric layer 106 is deposited over the barrier layer 102 .
- the dielectric materials that can be used to deposit 106 have been described above.
- the substrate is patterned and etched to create metal trenches 106 .
- FIG. 2B shows that after the formation of metal trenches 116 , a metallic barrier layer 130 is deposited to line metal trench 116 .
- FIG. 2C shows that after the barrier layer 130 is deposited, a copper layer 132 is deposited over the barrier layer 130 .
- the barrier layer 130 can be made of tantalum nitride (TaN), tantalum (Ta), Ru, or a combination of these films.
- a copper film 132 is then deposited to fill the metal trench 116 .
- barrier layer such as Ta, TaN or Ru
- barrier layer can form Ta x O y (Tantalum oxide), TaO x N y (Tantalum oxynitride), or RuO 2 (Ruthenium oxide).
- Electroless deposition of a metal layer on a substrate is highly dependent upon the surface characteristics and composition of the substrate. Electroless plating of copper on a Ta, TaN, or Ru surface is of interest for both seed layer formation prior to electroplating, and selective deposition of Cu lines within lithographically defined pattern(s). As described above, the concern is the inhibition of the electroless deposition process by atomically thin native metal oxide layer formed in the presence of oxygen (O 2 ).
- barrier oxide layer such as tantalum oxide, tantalum oxynitride, or ruthenium oxide
- pure barrier metal or barrier-layer-rich film such as Ta, Ru, or Ta-rich TaN film.
- barrier metal or barrier-layer-rich film such as Ta, Ru, or Ta-rich TaN film.
- Ta, Ru, or Ta-rich TaN film As described above, poor adhesion can negatively affect the EM performance.
- the formation tantalum oxide or tantalum oxynitride on the barrier layer surface can also increase the resistivity of the barrier layer. Due to these issues, it is desirable to use the integrated system to prepare the barrier/copper interface to ensure good adhesion between the barrier layer and copper and to ensure low resistivity of the barrier layer.
- FIG. 3A shows an embodiment of a process flow 300 of preparing a barrier (or liner) layer surface for electroless copper deposition after the trenches, such as trenches 116 of FIG. 2A ) have been formed.
- Forming metal trench interconnect over contact plugs, as shown in FIG. 2A-2C is merely used as an example.
- the concept of the invention can also be used to form dual-damascene interconnect structures over metal trenches, such as the ones shown in FIGS. 1A-1D , or other applicable interconnect structures.
- the barrier (or liner) layer may be prepared separately in a non-integrated deposition system, such as an ALD or PVD deposition reactor.
- the surface preparation for depositing a thin copper seed layer would not include the metal plug preclean and barrier deposition process steps.
- the top surface 124 a of the contact plug is cleaned to remove native metal oxide.
- Metal oxide can be removed by an Ar sputtering process, a plasma process using a fluorine-containing gas, such as NF 3 , CF 4 , or a combination of both, a wet chemical etch process, or a reduction process, for example using a hydrogen-containing plasma.
- Metal oxide can be removed by a wet chemical removal process in a 1-step or a 2-step wet chemical process sequence.
- the wet chemical removal process can use an organic acid, such as DeerClean offered by Kanto Chemical Co., Inc.
- a semi-aqueous solvent such as ESC 5800 offered by DuPont of Wilmington, Del.
- an organic base such as tetramethylammonium chloride (TMAH), complexing amines such as ethylene diamine, diethylene triamine, or proprietary chemistry such as ELD clean and Cap Clean 61, provided by Enthone, Inc. of West Haven, Conn.
- TMAH tetramethylammonium chloride
- complexing amines such as ethylene diamine, diethylene triamine, or proprietary chemistry such as ELD clean and Cap Clean 61, provided by Enthone, Inc. of West Haven, Conn.
- metal oxides specifically copper oxide, can be removed using a weak organic acid such as citric acid, or other organic or inorganic acids can be used.
- very dilute (i.e. ⁇ 0.1%) peroxide-containing acids such as sulfuric-peroxide mixtures, can also be used.
- a barrier layer is deposited. Due to the shrinking metal line and via critical dimension, the barrier layer may be deposited by atomic layer deposition (ALD), depending on the technology node.
- the thickness of the barrier layer 130 is between about 20 angstroms to about 200 angstroms. As described above, preventing the barrier layer from exposure to oxygen is critical in ensuring that electroless copper is being deposited on the barrier layer with good adhesion between copper and the barrier layer.
- the substrate should be transferred or processed in a controlled-ambient environment to limit exposure to oxygen.
- the barrier layer is hydrogen-plasma treated to produce a metal-rich surface on the barrier layer, such as Ta, TaN, or Ru, at step 305 to provide a catalytic surface for the subsequent copper seed deposition step.
- the reducing plasma can include gas, such as hydrogen or ammonia.
- the reducing plasma can include an inert gas, such as Ar, or He.
- Step 305 is an optional step, if the barrier surface is metal-rich after barrier layer deposition, such as the deposited barrier layer is a tantalum or ruthenium layer, the surface reduction step is not required.
- the barrier layer deposited is a barrier nitride layer, such as TaN, or if the barrier layer is exposed to oxygen, the hydrogen-plasma treatment (or reduction) would be needed. Whether this step is needed or not depends on how metal-rich the surface is.
- conformal copper seed is deposited on the barrier surface at step 307 , followed by a thick copper gap fill (or bulk fill) process, 308 .
- the conformal copper seed layer can be deposited by an electroless process.
- the thick copper bulk fill process can be an electroless deposition (ELD) process or an electrochemical plating (ECP) process.
- Electroless copper deposition and ECP are well-known wet process.
- the reactor needs to be integrated with a rinse/dryer to enable dry-in/dry-out process capability.
- the system needs to be filled with inert gas to ensure minimal exposure of the substrate to oxygen.
- the electroless deposition process can be carried out in a number of ways, such as puddle-plating, where fluid is dispensed onto a substrate and allowed to react in a static mode, after which the reactants are removed and discarded, or reclaimed.
- a dry-in/dry-out electroless copper process has been developed.
- the process uses a proximity process head to limit the electroless process liquid in contacting with the substrate surface on a limited region.
- the substrate surface not under the proximity process head is dry. Details of such process and system can be found in U.S. application Ser. No. 10/607,611, titled “Apparatus And Method For Depositing And Planarizing Thin Films On Semiconductor Wafers,” filed on Jun. 27, 2003, and U.S. application Ser.
- the substrate can undergo an optional substrate cleaning at step 309 .
- Post-copper-deposition clean can be accomplished by using a brush scrub clean with a chemical solution, such as a solution containing CP72B supplied by Air Products and Chemical, Inc. of Allentown, Pa.
- a chemical solution such as a solution containing CP72B supplied by Air Products and Chemical, Inc. of Allentown, Pa.
- Other substrate surface cleaning processes can also be used, such as Lam's C3TM or AMCTM (Advanced Mechanical Clean) cleaning technology.
- FIG. 3B shows an embodiment of a schematic diagram of an integrated system 350 that allows minimal exposure of substrate surface to oxygen at critical steps after barrier surface preparation.
- the substrate is transferred from one process station immediately to the next process station, limiting the duration that clean barrier surface is exposed to low levels of oxygen.
- the integrated system 350 can be used to process substrate(s) through the entire process sequence of flow 300 of FIG. 3A .
- the surface preparation for electroless deposition of copper and the optional post-cobalt-alloy deposition processes involves a mixture of dry and wet processes.
- the wet processes are typically operated near atmosphere, while the dry plasma processes are operated at less than 1 Torr.
- the substrate should be exposed to oxygen as little as possible, which can be achieved by being transferred and processed in controlled environment. Therefore, the integrated system needs to be able to handle a mixture of dry and wet processes.
- the reactor needs to be integrated with a rinse/dryer to enable dry-in/dry-out process capability.
- the integrated system 350 has 3 substrate transfer modules 360 , 370 , and 380 .
- Transfer modules 360 , 370 and 380 are equipped with robots to move substrate 355 from one process area to another process area.
- the process area could be a substrate cassette, a reactor, or a loadlock.
- Substrate transfer module 360 is operated under lab ambient. Module 360 interfaces with substrate loaders (or substrate cassettes) 361 to bring the substrate 355 into the integrated system or to return the substrate to one of the cassettes 361 .
- the substrate 355 is brought to the integrated system 350 to deposit barrier layer and copper layer.
- top tungsten surface 124 a of contact 125 is etched to remove native tungsten oxide. Once the tungsten oxide is removed, the exposed tungsten surface 124 a of FIG. 2A needs to be protected from exposure to oxygen.
- the removal process is an Ar sputtering process
- the reactor 371 is coupled to the vacuum transfer module 370 . If a wet chemical etching process is selected, the reactor should be coupled to the controlled-ambient transfer module 1080 , not the lab-ambient transfer module 360 , to limit exposure of the tungsten surface to oxygen.
- the substrate is deposited with a metallic barrier layer, such as Ta, TaN, Ru, or a combination of these films, as described in step 303 of FIG. 3A .
- the barrier layer 130 of FIG. 2B can be deposited by an ALD process or a PVD process.
- the ALD process is operated at less than 1 Torr.
- the ALD reactor 373 is coupled to the vacuum transfer module 370 .
- the deposition process is a high-pressure process using supercritical CO 2 and organo-metallic precursors to form the metal barrier.
- the deposition process is a physical vapor deposition (PVD) process operating at pressures less than 1 Torr.
- PVD physical vapor deposition
- the substrate can undergo an optional reduction (hydrogen-plasma treatment) process, for example using a hydrogen-containing plasma, as described in step 305 of FIG. 3A .
- the hydrogen reduction reactor 374 can be coupled to the vacuum transfer module 370 .
- the substrate is ready for electroless copper deposition.
- the electroless copper plating can be performed in an electroless copper-plating reactor 381 to deposit a conformal seed layer.
- copper bulk fill can be performed in the same electroless copper deposition reactor 381 used to deposit the conformal seed layer, but with a different chemistry to achieve bulk fill.
- copper bulk fill can be performed in a separate ECP reactor 381 ′.
- the substrate Before the substrate leaves the integrated system 350 , the substrate can optionally undergo a surface cleaning process, which can clean residues from the previous copper deposition process.
- the substrate cleaning process can be brush clean process.
- Substrate cleaning reactor 383 can be integrated with the controlled-ambient transfer module 380 .
- the substrate-cleaning reactor 383 can also be integrated with the lab-ambient transfer module 360 .
- the barrier layer 130 of FIG. 2B can be deposited in a process chamber before the substrate 200 is brought into a system for surface treatment and depositing copper.
- the process flow 300 described in FIG. 3A and system 350 described in FIG. 3B can also be used to deposit barrier layer and copper for dual damascene structures, as shown in FIGS. 1A-1D , or other applicable interconnect structures.
- step 301 in flow 300 is replaced by cleaning top surface of metal line, which is shown as surface 122 a of FIG. 1A .
- EM performance is affected by the quality of adhesion between copper and the barrier layer.
- chemical-grafting chemicals that would selectively bond to conducting or semi-conducting clean surfaces to form a self-assembled monolayer (SAM) of such chemicals on the conducting or semi-conducting clean surfaces.
- SAM self-assembled monolayer
- the electro-grafting or chemical-grafting chemical which is a complexing group and forms a monolayer on a conducting or a semiconducting surface, functionalizes the substrate surface to be deposited with a layer of material over the monolayer with strong bonding between the monolayer and the deposited layer material. Therefore, the monolayer can also be called a functionalization layer. From hereon, the terms self-assembled monolayer and functionalization layer are used interchangeably.
- the monolayer can be replaced by the deposited material during deposition process.
- the deposited material forms strong bonding directly with the substrate.
- the complexing group has one end that forms a covalent bond with the conducting or semiconducting surface.
- the complexing group of the funcationalization layer has one end forming a strong bond with Ta and another end forming a strong bond with copper, or can be modified to a catalytic site that will bond with copper.
- the chemical-grafting molecules are adsorbed by physisorption and chemisorption from the solution onto solid substrates to bond with the surface and to form ordered and a molecular functionalization layer, which is a self-assembled monolayer.
- FIG. 4A shows a bather layer 401 with a bather surface 410 .
- FIG. 4B shows that the barrier surface 410 is deposited with a functionalization layer 402 of the chemical-grafting complexing group 420 .
- the complexing group 420 has two ends, “A” end and “B” end. “A” end forms a covalent bond with the surface 410 with barrier metal.
- the complexing group 420 should have an “A” end that would form a covalent bond with the barrier surface, which could be made of materials, such as Ta, TaN, Ru, or other application materials.
- the “B” end form a covalent bond with the copper seed layer 403 , as shown in FIG. 4C .
- the “B” end of the complexing group 420 should choose a compound that would form a covalent bond with copper.
- copper 403 ′ replaces the entire complexing group 420 to deposit directly on the bather surface, as shown in FIG. 4D . or can be modified to a catalytic site that will bond with copper.
- the complexing group 420 in the FIG. 4D assist the copper in bonding to the barrier surface.
- the “A”-end of the chemical-grafting complexing group is a Lewis acid that interacts (or grafts) with a Lewis base barrier surface to form a bond between the metal and the chemical-grafting chemical (or complexing group).
- Examples of chemical-grafting complexing (or functional) group includes thiols, silanes, alcohols, organic acids, amine, and pyrrole.
- thiols examples include alkanethiols, such as decanethiol and octadecanethiol, tetraphenylporphines, diphenyl disulfide, aromatic thioacetate, ruthenium (II) tris(2,2, prime-biphyridine)thiol, thiophenol, 4,4 prime-dithiodipyridine, naphthalene disulfide, and bis(2-anthraquinyl) disulfide.
- alkanethiols such as decanethiol and octadecanethiol
- tetraphenylporphines diphenyl disulfide
- aromatic thioacetate examples include ruthenium (II) tris(2,2, prime-biphyridine)thiol, thiophenol, 4,4 prime-dithiodipyridine, naphthalene disulfide, and bis
- silanes include 3-mercaptoprophyl trimethoxysilane, ⁇ -methacryloxypropyl triethoxysilane, perfluoroctanoxylprophy-dimethyl silane, alkyltrichlorosilane, and oxtadecylsiloxane.
- An example of alcohols includes octanol.
- Examples of organic acids include 22-mercapto-1-docosanoic acid, alkanephosphonic acids, and octadecanoic acid.
- An example of amine includes diaminododecane.
- pyrrole include n-phenylpyrrole, and 2,5-dithienylpyrrol triad.
- the “B” end should be functional groups that contain elements that selectively bond to Cu. Such elements include copper (Cu), cobalt (Co), and ruthenium (Ru).
- FIG. 5A shows an opening 510 of an interconnect metal structure (metal 1 ) that is surrounded by a dielectric layer 501 .
- FIG. 5B shows that a barrier layer 502 is deposited to line the metal opening 510 .
- the bottom of the metal structure is a contact, which is similar to the contact 125 shown in FIG. 2A-2C .
- the barrier layer can be deposited by ALD, PVD, or other applicable processes.
- the thickness of the barrier layer is between about 5 angstroms to about 300 angstroms.
- FIG. 5C shows that a functionalization layer 503 of chemical-grating complexing compound is deposited on barrier layer 502 . In one embodiment, the thickness of the functionalization layer 503 is between about 5 angstroms to about 20 angstroms.
- a copper seed layer 504 is deposited over the functionalization layer 503 , as shown in FIG. 5D .
- copper gap-fill layer 505 is deposited, as shown in FIG. 5E .
- FIG. 6A shows an embodiment of a process flow of preparing the barrier (or liner) layer surface for electroless copper deposition.
- the top surface 125 a of contact 125 of FIG. 2A is cleaned to remove native metal oxide.
- Metal oxide can be removed by an Ar sputtering process or a wet chemical etch process.
- a barrier layer is deposited in either an ALD or a PVD system. As described above, preventing the bather layer from exposure to oxygen is critical in ensuring that electroless copper is being deposited on the barrier layer with good adhesion between copper and the bather layer. Similarly, for the functionalization layer to be properly deposited on the barrier surface, the barrier surface should be removed of the barrier oxide.
- the substrate should be transferred or processed in a controlled-ambient environment to limit exposure to oxygen.
- the barrier layer is treated by a reducing plasma (i.e. hydrogen-containing) at step 605 to produce a metal-rich layer that will provide a catalytic surface for the subsequent functionalization layer deposition step.
- the reducing plasma treatment is optional, depending on the composition of the surface.
- the substrate surface is deposited with a functionalization layer of chemical-grafting complexing compound at step 606 .
- the chemical-grafting complexing compound is mixed in a solution and the deposition process is a wet process.
- An optional clean step 607 after the deposition step at 606 may be needed.
- a conformal copper seed is deposited on the barrier surface at step 608 , followed by a thick copper bulk fill (or gap fill) process, 609 .
- the conformal copper seed layer can be deposited by an electroless process.
- the thick copper bulk fill (also gap fill) layer can be deposited by an ECP process.
- the thick bulk fill (also gap fill) layer can be deposited by an electroless process in the same electroless system for conformal copper seed, but with a different chemistry.
- next process step 610 is an optional substrate-cleaning step to clean any residual contaminants from the previous electroless cobalt-alloy deposition.
- FIG. 6B shows an embodiment of a schematic diagram of an integrated system 650 that allows minimal exposure of substrate surface to oxygen at critical steps after barrier and copper surface preparation.
- the substrate is transferred from one process station immediately to the next process station, which limits the duration that clean copper surface is exposed to low levels of oxygen.
- the integrated system 650 can be used to process substrate(s) through the entire process sequence of flow 600 of FIG. 6A .
- the integrated system 650 has 3 substrate transfer modules 660 , 670 , and 680 .
- Transfer modules 660 , 670 and 680 are equipped with robots to move substrate 655 from one process area to another process area.
- the process area could be a substrate cassette, a reactor, or a loadlock.
- Substrate transfer module 660 is operated under lab ambient. Module 660 interfaces with substrate loaders (or substrate cassettes) 661 to bring the substrate 655 into the integrated system or to return the substrate to one of the cassettes 661 .
- the substrate 655 is brought to the integrated system 650 to deposit barrier layer, to prepare barrier surface for copper layer deposition.
- top contact surface 125 a of contacts 125 is etched to remove native metal oxide. Once the metal oxide is removed, the exposed tungsten surface 125 a of FIG. 2A needs to be protected from exposure to oxygen. If the removal process is an Ar sputtering process, the Ar sputtering reactor 671 is coupled to the vacuum transfer module 670 .
- the reactor should be coupled to the controlled-ambient transfer module 680 , not the lab-ambient transfer module 660 , to limit the exposure of the clean tungsten surface to oxygen.
- the reactor needs to be integrated with a rinse/dryer to enable dry-in/dry-out process capability.
- the system needs to be filled with inert gas to ensure minimal exposure of the substrate to oxygen.
- the substrate is deposited with the barrier layer.
- the barrier layer 130 of FIG. 2B can be deposited by a PVD or an ALD process.
- the bather layer 130 is deposited by an ALD process, which is a dry process and is operated at less than 1 Torr.
- the ALD reactor 672 is coupled to the vacuum transfer module 670 .
- the substrate can undergo an optional hydrogen reduction process to ensure the barrier layer surface is metal-rich for functionalization layer deposition.
- the hydrogen reduction reactor 674 can be coupled to the vacuum transfer module 670 . At this stage, the substrate is ready for chemical-grafting complexing compound functionalization layer deposition.
- this process is a wet process and can be deposited in a chemical-grafting complexing compound deposition chamber 683 , coupled to the controlled-ambient transfer module 680 .
- chamber 683 is integrated a cleaning module (not shown) to clean the substrate 655 after the functionalization layer deposition.
- substrate 655 undergoes an optional substrate cleaning step 607 , as described in process flow 600 .
- the substrate cleaning process can be a brush clean process, whose reactor 685 can be integrated with the controlled-ambient transfer module 680 .
- substrate 655 is ready for copper seed layer deposition, as described in step 608 of flow 600 .
- the copper seed layer deposition is performed by an electroless process.
- the electroless copper plating can be performed in an electroless copper plating reactor 681 to deposit a conformal copper seed layer, as described in step 608 of FIG. 6A .
- the deposition of the gap fill copper layer at step 609 of FIG. 6A can be deposited in the same electroless plating reactor 681 with different chemistry, or in a separate ECP reactor 681 ′.
- the substrate Before the substrate leaves the integrated system 650 , the substrate can optionally undergoes a surface cleaning process, which can clean residues from the previous copper plating process.
- the substrate cleaning process can be brush clean process, whose reactor 663 can be integrated with the lab-ambient transfer module 660 .
- the wet processing systems described in FIG. 6B which are coupled to the controlled-ambient transfer module 680 , all need to meet the requirement of dry-in/dry-out to allow system integration.
- the systems are filled with one or more inert gases to ensure minimal exposure of the substrate to oxygen.
- step 601 in flow 600 is replaced by cleaning top surface of metal line, which is shown as surface 122 a of FIG. 1A .
- the embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect.
- the adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition.
- a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer.
- An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide.
- the method also includes depositing the functionalization layer over the metallic layer in the integrated system.
- the method further includes depositing the copper layer in the copper interconnect structure in the integrated system after the functionalization layer is deposited over the metallic barrier layer.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method is provided, including the following method operations: depositing a metallic barrier layer to line a copper interconnect structure by a dry process in an integrated system configured to operate a mixture of dry and wet processes; depositing the functionalization layer over the metallic barrier layer by a wet process in the integrated system; and, depositing the copper layer over the functionalization layer in the copper interconnect structure by a wet process in the integrated system after the functionalization layer is deposited over the metallic barrier layer, wherein the material used for the functionalization layer comprises a complexing group with at least two ends, one end of the complexing group forming a bond with the metallic barrier layer and another end of the complexing group forming a bond with the copper layer.
Description
- This application is a continuation of U.S. patent application Ser. No. 11/639,050, titled “Methods and Apparatus for Barrier Interface Preparation of Copper Interconnect,” filed on Dec. 13, 2006, which is a continuation-in-part of U.S. patent application Ser. No. 11/514,038, titled “Processes and Systems for Engineering A Barrier Surface for Copper Deposition,” filed on Aug. 30, 2006 (now U.S. Pat. No. 8,241,701 B2, issued on Aug. 14, 2012), the disclosures of which are incorporated by reference herein.
- This application is related to U.S. patent application Ser. No. 11/639,012, filed on Dec. 13, 2006, entitled “Self Assembled Monolayer for Improving Adhesion Between Copper and Barrier Layer.” The disclosure of this related application is incorporated herein by reference in its entirety for all purposes.
- Integrated circuits use conductive interconnects to wire together the individual devices on a semiconductor substrate, or to communicate externally to the integrated circuit. Interconnect metallization for vias and trenches may include aluminum alloys and copper. As device geometry continued to scale down to 65-nm-node technology and sub-65-nm technology, the requirement of continuous barrier/seed layer with good step coverage along high aspect ratio geometry to provide void free copper filling becomes challenging. The motivation to go to ultra thin and conformal barrier in 65-nm-node or sub-65-nm-technology is to reduce the barrier's impact on via and line resistance. However, poor adhesion of copper to the barrier layer could cause delamination between the barrier layer and copper during processing or thermal stressing that poses a concern on electro-migration and stress-induced voiding.
- In view of the foregoing, there is a need for systems and processes that enable deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect with good electro-migration performance and with reduced risk of stress-induce voiding of copper interconnect.
- Broadly speaking, the embodiments fill the need enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect with good electro-migration performance and with reduced risk of stress-induce voiding of copper interconnect. Electromigration and stress-induced voiding are affected by the adhesion between the barrier layer and the copper layer, which can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect. The functionalization layer forms strong bonds with barrier layer and with copper to improve adhesion property between the two layers. The functionalization layer can also merely enable the deposition of copper over the barrier layer and be replaced by the copper layer. It should be appreciated that the present invention can be implemented in numerous ways, including as a solution, a method, a process, an apparatus, or a system. Several inventive embodiments of the present invention are described below.
- In one embodiment, a method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided. The method includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method also includes depositing the functionalization layer over the metallic layer in the integrated system. The method further includes depositing the copper layer in the copper interconnect structure in the integrated system after the functionalization layer is deposited over the metallic barrier layer.
- In another embodiment, an integrated system for processing a substrate in controlled environment to enable deposition of a functionalization layer over a metallic barrier layer of a copper interconnect to improve electromigration performance of the copper interconnect is provided. The system includes a lab-ambient transfer chamber capable of transferring the substrate from a substrate cassette coupled to the lab-ambient transfer chamber into the integrated system. The system also includes a vacuum transfer chamber operated under vacuum at a pressure less than 1 Torr. The method further includes a vacuum process module for depositing the metallic barrier layer, wherein the vacuum process module for depositing the metallic barrier layer is coupled to the vacuum transfer chamber, and is operated under vacuum at a pressure less than 1 Torr. In addition, the method includes a controlled-ambient transfer chamber filled with an inert gas selected from a group of inert gases, and a deposition process module used to deposit the functionalization layer on the surface of the metallic barrier layer, wherein the deposition process module used to deposit the functionalization layer is coupled to the controlled-ambient transfer chamber.
- Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
- The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements.
-
FIGS. 1A-1D show cross sections of a dual-damascene interconnect structure at various stages of interconnect processing. -
FIGS. 2A-2C show cross sections of a metal line structure at various stages of interconnect processing. -
FIG. 3A shows an exemplary process flow of interconnect processing. -
FIG. 3B shows an exemplary integrated system used to process a substrate using a process flow ofFIG. 3A . -
FIGS. 4A-4D show cross sections of a metal line structure at various stages of interconnect processing to incorporate a functionalization layer. -
FIGS. 5A-5E show cross sections of an interconnect structure at various stages of interconnect processing to incorporate a functionalization layer. -
FIG. 6A shows an exemplary process flow of interconnect processing that incorporates a functionalization layer. -
FIG. 6B shows an exemplary integrated system used to process a substrate using a process flow ofFIG. 6A . - Several exemplary embodiments for improved metal integration techniques that remove interfacial metal oxide by reduction or add an adhesion-promoting layer to improve interface adhesion and to lower the resistivity of metal interconnect are provided. It should be appreciated that the present invention can be implemented in numerous ways, including a process, a method, an apparatus, or a system. Several inventive embodiments of the present invention are described below. It will be apparent to those skilled in the art that the present invention may be practiced without some or all of the specific details set forth herein.
-
FIG. 1A shows an exemplary cross-section of an interconnect structure(s) after being patterned by using a dual damascene process sequence. The interconnect structure(s) is on asubstrate 50 and has adielectric layer 100, which was previously fabricated to form ametallization line 101 therein. The metallization line is typically fabricated by etching a trench into the dielectric 100 and then filling the trench with a conductive material, such as copper. - In the trench, there is a
barrier layer 120, used to prevent thecopper material 122, from diffusing into the dielectric 100. Thebarrier layer 120 can be made of physical vapor deposition (PVD) tantalum nitride (TaN), PVD tantalum (Ta), atomic layer deposition (ALD) TaN, or a combination of these films. Other barrier layer materials can also be used. Abarrier layer 102 is deposited over theplanarized copper material 122 to protect thecopper material 122 from premature oxidation when viaholes 114 are etched through overlyingdielectric materials barrier layer 102. Thebarrier layer 102 is also configured to function as a selective etch stop.Exemplary barrier layer 102 materials include silicon nitride (SiN) or silicon carbide (SiC). - A via
dielectric layer 104 is deposited over thebarrier layer 102. The viadielectric layer 104 can be made of an organo-silicate glass (OS G, carbon-doped silicon oxide) or other types of dielectric materials, preferably with low dielectric constants. Exemplary silicon dioxides can include, a PECVD un-doped TEOS silicon dioxide, a PECVD fluorinated silica glass (FSG), a HDP FSG, OSG, porous OSG, etc. and the like. Commercially available dielectric materials including Black Diamond (I) and Black Diamond (II) by Applied Materials of Santa Clara, Calif., Coral by Novellus Systems of San Jose, Aurora by ASM America Inc. of Phoenix, Ariz., can also be used. Over the viadielectric layer 104 is atrench dielectric layer 106. Thetrench dielectric layer 106 may be a low K dielectric material, such as a carbon-doped oxide (C-oxide). The dielectric constant of the low K dielectric material can be about 3.0 or lower. In one embodiment, both the via and trench dielectric layers are made of the same material, and deposited at the same time to form a continuous film. After thetrench dielectric layer 106 is deposited, thesubstrate 50 that holds the structure(s) undergoes patterning and etching processes to form the vias holes 114 andtrenches 116 by known art. -
FIG. 1B shows that after the formation ofvias holes 114 andtrenches 116, abarrier layer 130 and acopper layer 132 are deposited to line and fill the via holes 114 and thetrenches 116. Thebarrier layer 130 can be made of tantalum nitride (TaN), tantalum (Ta), Ruthenium (Ru), or a hybrid combination of these materials. While these are the commonly considered materials, other barrier layer materials can also be used. Barrier layer materials may be other refractory metal compound including but not limited to titanium (Ti), tungsten (W), zirconium (Zr), hafnium (Hf), molybdenum (Mo), niobium (Nb), vanadium (V), ruthenium (Ru) and chromium (Cr), among others. - A
copper film 132 is then deposited to fill the via holes 114 and thetrenches 116, as shown inFIG. 1C . In one embodiment, thecopper film 132 includes a thincopper seed layer 131 underneath. In one embodiment, the thickness of the thin copper seed layer is between about 5 angstroms to about 300 angstroms. - Barrier layer, such as Ta, TaN or Ru, if exposed to air for extended period of time, can form TaxOy (Tantalum oxide), TaOxNy (Tantalum oxynitride), or RuO2 (Ruthenium oxide). Electroless deposition of a metal layer on a substrate is highly dependent upon the surface characteristics and composition of the substrate. Electroless plating of copper on a Ta, TaN, or Ru surface is of interest for both seed layer formation prior to electroplating, and selective deposition of Cu lines within lithographically defined pattern(s). One concern is the inhibition of the electroless deposition process by atomically thin native metal oxide layer formed in the presence of oxygen (O2).
- In addition, copper film does not adhere to the barrier oxide layer, such as tantalum oxide, tantalum oxynitride, or ruthenium oxide, as well as it adheres to the pure barrier metal or barrier-layer-rich film, such as Ta, Ru, or Ta-rich TaN film. Ta and/or TaN barrier layers are only used as examples. The description and concept apply to other types of barrier metals, such as Ta or TaN capped with a thin layer of Ru. As described above, poor adhesion can negatively affect the EM performance. In addition, the formation tantalum oxide or tantalum oxynitride on the barrier layer surface can increase the resistivity of the barrier layer. Due to these issues, it is desirable to use the integrated system to prepare the barrier/copper interface to ensure good adhesion between the barrier layer and copper and to ensure low resistivity of the barrier layer.
-
FIG. 1B shows that thebarrier layer 130 is a single layer deposited either by ALD or PVD. Alternatively, thebarrier layer 130 can be deposited by an ALD process to deposit afirst barrier layer 130 I, such as TaN, which is followed by a PVDsecond barrier layer 130 II, such as Ta, as shown inFIG. 1D . - In addition to dual-damascene interconnect structures, copper interconnect can also be applied to metal lines (or M1 lines) over contacts.
FIG. 2A shows an exemplary cross-section of a metal line structure after being patterned by a dielectric etch and being removed of photoresist. The metal line structure(s) is on asubstrate 200 and has asilicon layer 110, which was previously fabricated to form agate structure 105 with agate oxide 121,spacers 107 and acontact 125 therein. Thecontact 125 is typically fabricated by etching a contact hole into theoxide 103 and then filling the contact hole with a conductive material, such as tungsten. Alternative materials may include copper, aluminum or other conductive materials. Thebarrier layer 102 is configured to function as a selective trench etch stop. Thebarrier layer 102 can be made of materials such as silicon nitride (SiN) or silicon carbide (SiC). - A metal
line dielectric layer 106 is deposited over thebarrier layer 102. The dielectric materials that can be used to deposit 106 have been described above. After the deposition ofdielectric layer 106, the substrate is patterned and etched to createmetal trenches 106.FIG. 2B shows that after the formation ofmetal trenches 116, ametallic barrier layer 130 is deposited to linemetal trench 116.FIG. 2C shows that after thebarrier layer 130 is deposited, acopper layer 132 is deposited over thebarrier layer 130. Similar to the dual-damascene interconnect structures, thebarrier layer 130 can be made of tantalum nitride (TaN), tantalum (Ta), Ru, or a combination of these films. Acopper film 132 is then deposited to fill themetal trench 116. - As described above for dual-damascene structures, barrier layer, such as Ta, TaN or Ru, if exposed to air for extended period of time, can form TaxOy (Tantalum oxide), TaOxNy (Tantalum oxynitride), or RuO2 (Ruthenium oxide). Electroless deposition of a metal layer on a substrate is highly dependent upon the surface characteristics and composition of the substrate. Electroless plating of copper on a Ta, TaN, or Ru surface is of interest for both seed layer formation prior to electroplating, and selective deposition of Cu lines within lithographically defined pattern(s). As described above, the concern is the inhibition of the electroless deposition process by atomically thin native metal oxide layer formed in the presence of oxygen (O2). In addition, copper film does not adhere to the barrier oxide layer, such as tantalum oxide, tantalum oxynitride, or ruthenium oxide, as well as it adheres to the pure barrier metal or barrier-layer-rich film, such as Ta, Ru, or Ta-rich TaN film. As described above, poor adhesion can negatively affect the EM performance. The formation tantalum oxide or tantalum oxynitride on the barrier layer surface can also increase the resistivity of the barrier layer. Due to these issues, it is desirable to use the integrated system to prepare the barrier/copper interface to ensure good adhesion between the barrier layer and copper and to ensure low resistivity of the barrier layer.
-
FIG. 3A shows an embodiment of aprocess flow 300 of preparing a barrier (or liner) layer surface for electroless copper deposition after the trenches, such astrenches 116 ofFIG. 2A ) have been formed. Forming metal trench interconnect over contact plugs, as shown inFIG. 2A-2C , is merely used as an example. The concept of the invention can also be used to form dual-damascene interconnect structures over metal trenches, such as the ones shown inFIGS. 1A-1D , or other applicable interconnect structures. It should be noted, however, that the barrier (or liner) layer may be prepared separately in a non-integrated deposition system, such as an ALD or PVD deposition reactor. In this case, the surface preparation for depositing a thin copper seed layer would not include the metal plug preclean and barrier deposition process steps. Atstep 301, thetop surface 124 a of the contact plug is cleaned to remove native metal oxide. Metal oxide can be removed by an Ar sputtering process, a plasma process using a fluorine-containing gas, such as NF3, CF4, or a combination of both, a wet chemical etch process, or a reduction process, for example using a hydrogen-containing plasma. Metal oxide can be removed by a wet chemical removal process in a 1-step or a 2-step wet chemical process sequence. The wet chemical removal process can use an organic acid, such as DeerClean offered by Kanto Chemical Co., Inc. of Japan or a semi-aqueous solvent, such as ESC 5800 offered by DuPont of Wilmington, Del., an organic base such as tetramethylammonium chloride (TMAH), complexing amines such as ethylene diamine, diethylene triamine, or proprietary chemistry such as ELD clean and Cap Clean 61, provided by Enthone, Inc. of West Haven, Conn. In addition, metal oxides, specifically copper oxide, can be removed using a weak organic acid such as citric acid, or other organic or inorganic acids can be used. Additionally, very dilute (i.e. <0.1%) peroxide-containing acids, such as sulfuric-peroxide mixtures, can also be used. - At
step 303, a barrier layer is deposited. Due to the shrinking metal line and via critical dimension, the barrier layer may be deposited by atomic layer deposition (ALD), depending on the technology node. The thickness of thebarrier layer 130 is between about 20 angstroms to about 200 angstroms. As described above, preventing the barrier layer from exposure to oxygen is critical in ensuring that electroless copper is being deposited on the barrier layer with good adhesion between copper and the barrier layer. Once the barrier layer is deposited, the substrate should be transferred or processed in a controlled-ambient environment to limit exposure to oxygen. In one embodiment, the barrier layer is hydrogen-plasma treated to produce a metal-rich surface on the barrier layer, such as Ta, TaN, or Ru, atstep 305 to provide a catalytic surface for the subsequent copper seed deposition step. The reducing plasma can include gas, such as hydrogen or ammonia. The reducing plasma can include an inert gas, such as Ar, or He. Step 305 is an optional step, if the barrier surface is metal-rich after barrier layer deposition, such as the deposited barrier layer is a tantalum or ruthenium layer, the surface reduction step is not required. On the other hand, if the barrier layer deposited is a barrier nitride layer, such as TaN, or if the barrier layer is exposed to oxygen, the hydrogen-plasma treatment (or reduction) would be needed. Whether this step is needed or not depends on how metal-rich the surface is. - Afterwards, conformal copper seed is deposited on the barrier surface at
step 307, followed by a thick copper gap fill (or bulk fill) process, 308. In one embodiment, the conformal copper seed layer can be deposited by an electroless process. The thick copper bulk fill process can be an electroless deposition (ELD) process or an electrochemical plating (ECP) process. Electroless copper deposition and ECP are well-known wet process. For a wet process to be integrated in a system with controlled processing and transporting environment, the reactor needs to be integrated with a rinse/dryer to enable dry-in/dry-out process capability. In addition, the system needs to be filled with inert gas to ensure minimal exposure of the substrate to oxygen. The electroless deposition process can be carried out in a number of ways, such as puddle-plating, where fluid is dispensed onto a substrate and allowed to react in a static mode, after which the reactants are removed and discarded, or reclaimed. Recently, a dry-in/dry-out electroless copper process has been developed. The process uses a proximity process head to limit the electroless process liquid in contacting with the substrate surface on a limited region. The substrate surface not under the proximity process head is dry. Details of such process and system can be found in U.S. application Ser. No. 10/607,611, titled “Apparatus And Method For Depositing And Planarizing Thin Films On Semiconductor Wafers,” filed on Jun. 27, 2003, and U.S. application Ser. No. 10/879,263, titled “Method and Apparatus For Plating Semiconductor Wafers,” filed on Jun. 28, 2004, both of which are incorporated herein in their entireties. Further, all fluids used in the process are de-gassed, i.e. dissolved oxygen is removed by commercially available degassing systems. - After copper deposition at
steps step 309. Post-copper-deposition clean can be accomplished by using a brush scrub clean with a chemical solution, such as a solution containing CP72B supplied by Air Products and Chemical, Inc. of Allentown, Pa. Other substrate surface cleaning processes can also be used, such as Lam's C3™ or AMC™ (Advanced Mechanical Clean) cleaning technology. -
FIG. 3B shows an embodiment of a schematic diagram of anintegrated system 350 that allows minimal exposure of substrate surface to oxygen at critical steps after barrier surface preparation. In addition, since it is an integrated system, the substrate is transferred from one process station immediately to the next process station, limiting the duration that clean barrier surface is exposed to low levels of oxygen. Theintegrated system 350 can be used to process substrate(s) through the entire process sequence offlow 300 ofFIG. 3A . - As described above, the surface preparation for electroless deposition of copper and the optional post-cobalt-alloy deposition processes involves a mixture of dry and wet processes. The wet processes are typically operated near atmosphere, while the dry plasma processes are operated at less than 1 Torr. In addition, after the barrier layer has been deposited, the substrate should be exposed to oxygen as little as possible, which can be achieved by being transferred and processed in controlled environment. Therefore, the integrated system needs to be able to handle a mixture of dry and wet processes. For a wet process to be integrated in a system with controlled processing and transporting environment, the reactor needs to be integrated with a rinse/dryer to enable dry-in/dry-out process capability. In addition, the system needs to be filled with inert gas to ensure minimal exposure of the substrate to oxygen. The
integrated system 350 has 3substrate transfer modules Transfer modules substrate 355 from one process area to another process area. The process area could be a substrate cassette, a reactor, or a loadlock.Substrate transfer module 360 is operated under lab ambient.Module 360 interfaces with substrate loaders (or substrate cassettes) 361 to bring thesubstrate 355 into the integrated system or to return the substrate to one of thecassettes 361. - As described above in
process flow 300, thesubstrate 355 is brought to theintegrated system 350 to deposit barrier layer and copper layer. As described instep 301 ofprocess flow 300,top tungsten surface 124 a ofcontact 125 is etched to remove native tungsten oxide. Once the tungsten oxide is removed, the exposedtungsten surface 124 a ofFIG. 2A needs to be protected from exposure to oxygen. If the removal process is an Ar sputtering process, thereactor 371 is coupled to thevacuum transfer module 370. If a wet chemical etching process is selected, the reactor should be coupled to the controlled-ambient transfer module 1080, not the lab-ambient transfer module 360, to limit exposure of the tungsten surface to oxygen. - Afterwards, the substrate is deposited with a metallic barrier layer, such as Ta, TaN, Ru, or a combination of these films, as described in
step 303 ofFIG. 3A . Thebarrier layer 130 ofFIG. 2B can be deposited by an ALD process or a PVD process. In one embodiment, the ALD process is operated at less than 1 Torr. TheALD reactor 373 is coupled to thevacuum transfer module 370. In another embodiment, the deposition process is a high-pressure process using supercritical CO2 and organo-metallic precursors to form the metal barrier. In yet another embodiment, the deposition process is a physical vapor deposition (PVD) process operating at pressures less than 1 Torr. Details of an exemplary reactor for a high-pressure process using supercritical CO2 is described in commonly assigned application Ser. No. 10/357,664, titled “Method and Apparatus for Semiconductor Wafer Cleaning Using High-Frequency Acoustic Energy with Supercritical Fluid”, filed on Feb. 3, 2003, which in incorporated herein for reference. - The substrate can undergo an optional reduction (hydrogen-plasma treatment) process, for example using a hydrogen-containing plasma, as described in
step 305 ofFIG. 3A . Thehydrogen reduction reactor 374 can be coupled to thevacuum transfer module 370. At this stage, the substrate is ready for electroless copper deposition. The electroless copper plating can be performed in an electroless copper-platingreactor 381 to deposit a conformal seed layer. Following the seed layer deposition, copper bulk fill can be performed in the same electrolesscopper deposition reactor 381 used to deposit the conformal seed layer, but with a different chemistry to achieve bulk fill. Alternatively, copper bulk fill can be performed in aseparate ECP reactor 381′. - Before the substrate leaves the
integrated system 350, the substrate can optionally undergo a surface cleaning process, which can clean residues from the previous copper deposition process. For example, the substrate cleaning process can be brush clean process.Substrate cleaning reactor 383 can be integrated with the controlled-ambient transfer module 380. Alternatively, the substrate-cleaningreactor 383 can also be integrated with the lab-ambient transfer module 360. Alternatively, thebarrier layer 130 ofFIG. 2B can be deposited in a process chamber before thesubstrate 200 is brought into a system for surface treatment and depositing copper. As discussed above, theprocess flow 300 described inFIG. 3A andsystem 350 described inFIG. 3B can also be used to deposit barrier layer and copper for dual damascene structures, as shown inFIGS. 1A-1D , or other applicable interconnect structures. For dual damascene structures,step 301 inflow 300 is replaced by cleaning top surface of metal line, which is shown assurface 122 a ofFIG. 1A . - As described above, EM performance is affected by the quality of adhesion between copper and the barrier layer. In one embodiment, chemical-grafting chemicals that would selectively bond to conducting or semi-conducting clean surfaces to form a self-assembled monolayer (SAM) of such chemicals on the conducting or semi-conducting clean surfaces. The electro-grafting or chemical-grafting chemical, which is a complexing group and forms a monolayer on a conducting or a semiconducting surface, functionalizes the substrate surface to be deposited with a layer of material over the monolayer with strong bonding between the monolayer and the deposited layer material. Therefore, the monolayer can also be called a functionalization layer. From hereon, the terms self-assembled monolayer and functionalization layer are used interchangeably. Alternatively, the monolayer can be replaced by the deposited material during deposition process. The deposited material forms strong bonding directly with the substrate. The complexing group has one end that forms a covalent bond with the conducting or semiconducting surface. Using Ta as an example of barrier metal for copper interconnect, the complexing group of the funcationalization layer has one end forming a strong bond with Ta and another end forming a strong bond with copper, or can be modified to a catalytic site that will bond with copper. For SAM formed by chemical grafting, the chemical-grafting molecules are adsorbed by physisorption and chemisorption from the solution onto solid substrates to bond with the surface and to form ordered and a molecular functionalization layer, which is a self-assembled monolayer.
-
FIG. 4A shows abather layer 401 with abather surface 410.FIG. 4B shows that thebarrier surface 410 is deposited with afunctionalization layer 402 of the chemical-graftingcomplexing group 420. Thecomplexing group 420 has two ends, “A” end and “B” end. “A” end forms a covalent bond with thesurface 410 with barrier metal. Thecomplexing group 420 should have an “A” end that would form a covalent bond with the barrier surface, which could be made of materials, such as Ta, TaN, Ru, or other application materials. In one embodiment, the “B” end form a covalent bond with thecopper seed layer 403, as shown inFIG. 4C . In such embodiment, the “B” end of thecomplexing group 420 should choose a compound that would form a covalent bond with copper. Alternatively,copper 403′ replaces theentire complexing group 420 to deposit directly on the bather surface, as shown inFIG. 4D . or can be modified to a catalytic site that will bond with copper. Thecomplexing group 420 in theFIG. 4D assist the copper in bonding to the barrier surface. - In one embodiment, the “A”-end of the chemical-grafting complexing group is a Lewis acid that interacts (or grafts) with a Lewis base barrier surface to form a bond between the metal and the chemical-grafting chemical (or complexing group). Examples of chemical-grafting complexing (or functional) group includes thiols, silanes, alcohols, organic acids, amine, and pyrrole. Examples of thiols include alkanethiols, such as decanethiol and octadecanethiol, tetraphenylporphines, diphenyl disulfide, aromatic thioacetate, ruthenium (II) tris(2,2, prime-biphyridine)thiol, thiophenol, 4,4 prime-dithiodipyridine, naphthalene disulfide, and bis(2-anthraquinyl) disulfide. Examples of silanes include 3-mercaptoprophyl trimethoxysilane, γ-methacryloxypropyl triethoxysilane, perfluoroctanoxylprophy-dimethyl silane, alkyltrichlorosilane, and oxtadecylsiloxane. An example of alcohols includes octanol. Examples of organic acids include 22-mercapto-1-docosanoic acid, alkanephosphonic acids, and octadecanoic acid. An example of amine includes diaminododecane. Examples of pyrrole include n-phenylpyrrole, and 2,5-dithienylpyrrol triad. The “B” end should be functional groups that contain elements that selectively bond to Cu. Such elements include copper (Cu), cobalt (Co), and ruthenium (Ru).
-
FIG. 5A shows anopening 510 of an interconnect metal structure (metal 1) that is surrounded by adielectric layer 501.FIG. 5B shows that abarrier layer 502 is deposited to line themetal opening 510. The bottom of the metal structure is a contact, which is similar to thecontact 125 shown inFIG. 2A-2C . The barrier layer can be deposited by ALD, PVD, or other applicable processes. The thickness of the barrier layer is between about 5 angstroms to about 300 angstroms.FIG. 5C shows that afunctionalization layer 503 of chemical-grating complexing compound is deposited onbarrier layer 502. In one embodiment, the thickness of thefunctionalization layer 503 is between about 5 angstroms to about 20 angstroms. After thefunctionalization layer 503 is deposited, acopper seed layer 504 is deposited over thefunctionalization layer 503, as shown inFIG. 5D . Aftercopper seed layer 504 is deposited, copper gap-fill layer 505 is deposited, as shown inFIG. 5E . -
FIG. 6A shows an embodiment of a process flow of preparing the barrier (or liner) layer surface for electroless copper deposition. Atstep 601, the top surface 125 a ofcontact 125 ofFIG. 2A is cleaned to remove native metal oxide. Metal oxide can be removed by an Ar sputtering process or a wet chemical etch process. Atstep 603, a barrier layer is deposited in either an ALD or a PVD system. As described above, preventing the bather layer from exposure to oxygen is critical in ensuring that electroless copper is being deposited on the barrier layer with good adhesion between copper and the bather layer. Similarly, for the functionalization layer to be properly deposited on the barrier surface, the barrier surface should be removed of the barrier oxide. Once the barrier layer is deposited, the substrate should be transferred or processed in a controlled-ambient environment to limit exposure to oxygen. The barrier layer is treated by a reducing plasma (i.e. hydrogen-containing) atstep 605 to produce a metal-rich layer that will provide a catalytic surface for the subsequent functionalization layer deposition step. The reducing plasma treatment is optional, depending on the composition of the surface. Afterwards, the substrate surface is deposited with a functionalization layer of chemical-grafting complexing compound atstep 606. In one embodiment, the chemical-grafting complexing compound is mixed in a solution and the deposition process is a wet process. An optionalclean step 607 after the deposition step at 606 may be needed. - Afterwards, a conformal copper seed is deposited on the barrier surface at
step 608, followed by a thick copper bulk fill (or gap fill) process, 609. The conformal copper seed layer can be deposited by an electroless process. The thick copper bulk fill (also gap fill) layer can be deposited by an ECP process. Alternatively, the thick bulk fill (also gap fill) layer can be deposited by an electroless process in the same electroless system for conformal copper seed, but with a different chemistry. - After the substrate is deposited with conformal copper seed at
step 608, and thick Cu bulk fill by either an electroless or electro-plating process atstep 609, thenext process step 610 is an optional substrate-cleaning step to clean any residual contaminants from the previous electroless cobalt-alloy deposition. -
FIG. 6B shows an embodiment of a schematic diagram of anintegrated system 650 that allows minimal exposure of substrate surface to oxygen at critical steps after barrier and copper surface preparation. In addition, since it is an integrated system, the substrate is transferred from one process station immediately to the next process station, which limits the duration that clean copper surface is exposed to low levels of oxygen. Theintegrated system 650 can be used to process substrate(s) through the entire process sequence offlow 600 ofFIG. 6A . - The
integrated system 650 has 3substrate transfer modules Transfer modules substrate 655 from one process area to another process area. The process area could be a substrate cassette, a reactor, or a loadlock.Substrate transfer module 660 is operated under lab ambient.Module 660 interfaces with substrate loaders (or substrate cassettes) 661 to bring thesubstrate 655 into the integrated system or to return the substrate to one of thecassettes 661. - As described above in process flow 600 of
FIG. 6A , thesubstrate 655 is brought to theintegrated system 650 to deposit barrier layer, to prepare barrier surface for copper layer deposition. As described instep 601 ofprocess flow 600, top contact surface 125 a ofcontacts 125 is etched to remove native metal oxide. Once the metal oxide is removed, the exposed tungsten surface 125 a ofFIG. 2A needs to be protected from exposure to oxygen. If the removal process is an Ar sputtering process, theAr sputtering reactor 671 is coupled to thevacuum transfer module 670. If a wet chemical etching process is selected, the reactor should be coupled to the controlled-ambient transfer module 680, not the lab-ambient transfer module 660, to limit the exposure of the clean tungsten surface to oxygen. For a wet process to be integrated in a system with controlled processing and transporting environment, the reactor needs to be integrated with a rinse/dryer to enable dry-in/dry-out process capability. In addition, the system needs to be filled with inert gas to ensure minimal exposure of the substrate to oxygen. - Afterwards, the substrate is deposited with the barrier layer. The
barrier layer 130 ofFIG. 2B can be deposited by a PVD or an ALD process. In one embodiment, thebather layer 130 is deposited by an ALD process, which is a dry process and is operated at less than 1 Torr. TheALD reactor 672 is coupled to thevacuum transfer module 670. The substrate can undergo an optional hydrogen reduction process to ensure the barrier layer surface is metal-rich for functionalization layer deposition. Thehydrogen reduction reactor 674 can be coupled to thevacuum transfer module 670. At this stage, the substrate is ready for chemical-grafting complexing compound functionalization layer deposition. As described above, in one embodiment, this process is a wet process and can be deposited in a chemical-grafting complexingcompound deposition chamber 683, coupled to the controlled-ambient transfer module 680. In one embodiment,chamber 683 is integrated a cleaning module (not shown) to clean thesubstrate 655 after the functionalization layer deposition. In another embodiment,substrate 655 undergoes an optionalsubstrate cleaning step 607, as described inprocess flow 600. The substrate cleaning process can be a brush clean process, whosereactor 685 can be integrated with the controlled-ambient transfer module 680. After the substrate surface cleaning,substrate 655 is ready for copper seed layer deposition, as described instep 608 offlow 600. In one embodiment, the copper seed layer deposition is performed by an electroless process. The electroless copper plating can be performed in an electrolesscopper plating reactor 681 to deposit a conformal copper seed layer, as described instep 608 ofFIG. 6A . As described above, the deposition of the gap fill copper layer atstep 609 ofFIG. 6A can be deposited in the sameelectroless plating reactor 681 with different chemistry, or in aseparate ECP reactor 681′. - Before the substrate leaves the
integrated system 650, the substrate can optionally undergoes a surface cleaning process, which can clean residues from the previous copper plating process. The substrate cleaning process can be brush clean process, whosereactor 663 can be integrated with the lab-ambient transfer module 660. - The wet processing systems described in
FIG. 6B , which are coupled to the controlled-ambient transfer module 680, all need to meet the requirement of dry-in/dry-out to allow system integration. In addition, the systems are filled with one or more inert gases to ensure minimal exposure of the substrate to oxygen. - The process flow 600 described in
FIG. 6A andsystem 650 described inFIG. 6B can be used to deposit barrier layer and copper for dual damascene structures, as shown inFIGS. 1A-1D . For dual damascene structures,step 601 inflow 600 is replaced by cleaning top surface of metal line, which is shown assurface 122 a ofFIG. 1A . - The embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect. The adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided. The method includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method also includes depositing the functionalization layer over the metallic layer in the integrated system. The method further includes depositing the copper layer in the copper interconnect structure in the integrated system after the functionalization layer is deposited over the metallic barrier layer.
- While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention. In the claims, elements and/or steps do not imply any particular order of operation, unless explicitly stated in the claims.
Claims (20)
1. A method, comprising:
depositing a metallic barrier layer to line a copper interconnect structure by a dry process in an integrated system configured to operate a mixture of dry and wet processes;
depositing the functionalization layer over the metallic barrier layer by a wet process in the integrated system; and
depositing the copper layer over the functionalization layer in the copper interconnect structure by a wet process in the integrated system after the functionalization layer is deposited over the metallic barrier layer, wherein the material used for the functionalization layer comprises a complexing group with at least two ends, one end of the complexing group forming a bond with the metallic barrier layer and another end of the complexing group forming a bond with the copper layer.
2. The method of claim 1 , wherein the integrated system defines a controlled environment to prevent the formation of metallic barrier oxide after deposition of the metallic barrier layer, the controlled environment defined by a vacuum transfer module coupled to one or more dry process chambers and a controlled-ambient transfer module coupled to one or more wet process chambers, the vacuum transfer module and the controlled-ambient transfer module being coupled to each other so as to form a common path for the substrate to directly travel between the vacuum transfer module and the controlled-ambient transfer module.
3. The method of claim 2 , further comprising:
transporting the substrate from the vacuum transfer module to the controlled-ambient transfer module;
wherein the transfer modules transfer the substrate in a dry state from one process chamber to a next process chamber.
4. The method of claim 1 , wherein the functionalization layer between the metallic barrier layer and the copper layer assists the deposition of the copper layer and improves adhesion between the metallic barrier layer and the copper layer.
5. The method of claim 1 , further comprising:
cleaning an exposed surface of an underlying metal to the copper interconnect to remove a surface metal oxide of the exposed surface of the underlying metal in the integrated system before depositing the metallic barrier layer, wherein the underlying metal is part of an underlying interconnect electrically connected to the copper interconnect.
6. The method of claim 5 , wherein cleaning the exposed surface of the surface metal oxide is accomplished by using one of an Ar sputtering process or a plasma process using a fluorine-containing gas.
7. The method of claim 6 , wherein the fluorine-containing gas is NF3, CF4, or a combination of both.
8. The method of claim 1 , further comprising:
reducing a surface of the metallic barrier layer to make the surface of the metallic barrier layer metal-rich in the integrated system before depositing the functionalization layer.
9. The method of claim 8 , wherein reducing the surface of the metallic barrier layer is performed by using a hydrogen-containing plasma.
10. The method of claim 1 , wherein the material of the metallic barrier layer is selected from the group consisting of tantalum nitride (TaN), tantalum (Ta), Ruthenium (Ru), titanium (Ti), tungsten (W), zirconium (Zr), hafnium (Hf), molybdenum (Mo), niobium (Nb), vanadium (V), ruthenium (Ru) and chromium (Cr), and a hybrid combination of these materials.
11. The method of claim 1 , wherein the complexing group is selected from the group consisting of decanethiol, octadecanethiol, tetraphenylporphines, diphenyl disulfide, aromatic thioacetate, ruthenium (II) tris(2,2, prime-biphyridine)thiol, thiophenol, 4,4 prime-dithiodipyridine, naphthalene disulfide, and bis(2-anthraquinyl)disulfide, 3-mercaptoprophyl trimethoxysilane, γ-methacryloxypropyl triethoxysilane, perfluoroctanoxylprophy-dimethyl silane, alkyltrichlorosilane, oxtadecylsiloxane, octanol, 22-mercapto-1-docosanoic acid, alkanephosphonic acids, octadecanoic acid, diaminododecane, n-phenylpyrrole, and 2,5-dithienylpyrrol triad.
12. The method of claim 1 , wherein the copper interconnect is over an underlying interconnect which includes a metal line.
13. The method of claim 1 , wherein the copper interconnect is over an underlying interconnect which includes a contact.
14. The method of claim 1 , wherein depositing the metallic barrier layer further includes:
depositing a first metallic barrier layer; and
depositing a second metallic barrier layer.
15. The method of claim 14 , wherein the first metallic barrier layer is deposited by an atomic layer deposition (ALD) process and the second metallic barrier layer is deposited by a physical vapor deposition (PVD) process.
16. The method of claim 14 , wherein the first metallic barrier layer is deposited by an ALD process and the second metallic barrier layer is deposited by an ALD process.
17. The method of claim 1 , further comprising:
cleaning a surface of the functionalization layer in the integrated system before depositing the copper layer.
18. The method of clam 1, wherein the copper layer is a thin copper seed layer selectively deposited by an electroless process.
19. The method of claim 18 , wherein a gap-fill copper layer is deposited following the deposition of the thin copper seed layer by an electrochemical plating (ECP) process.
20. A method, comprising:
cleaning an exposed surface of an underlying metal to a copper interconnect to remove a surface metal oxide of the exposed surface of the underlying metal in an integrated system configured to operate a mixture of dry and wet processes before depositing a metallic barrier layer, wherein the underlying metal is part of an underlying interconnect electrically connected to the copper interconnect;
depositing the metallic barrier layer to line the copper interconnect structure by a dry process in the integrated system;
reducing a surface of the metallic barrier layer to make the surface of the metallic barrier layer metal-rich in the integrated system before depositing a functionalization layer;
depositing the functionalization layer over the metallic barrier layer by a wet process in the integrated system; and
depositing a copper layer over the functionalization layer in the copper interconnect structure by a wet process in the integrated system after the functionalization layer is deposited over the metallic barrier layer, wherein the material used for the functionalization layer comprises a complexing group with at least two ends, one end of the complexing group forming a bond with the metallic barrier layer and another end of the complexing group forming a bond with copper.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/558,548 US20150132946A1 (en) | 2006-08-30 | 2014-12-02 | Methods for barrier interface preparation of copper interconnect |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/514,038 US8241701B2 (en) | 2005-08-31 | 2006-08-30 | Processes and systems for engineering a barrier surface for copper deposition |
US11/639,012 US20090304914A1 (en) | 2006-08-30 | 2006-12-13 | Self assembled monolayer for improving adhesion between copper and barrier layer |
US11/639,050 US8916232B2 (en) | 2006-08-30 | 2006-12-13 | Method for barrier interface preparation of copper interconnect |
US14/558,548 US20150132946A1 (en) | 2006-08-30 | 2014-12-02 | Methods for barrier interface preparation of copper interconnect |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/639,050 Continuation US8916232B2 (en) | 2006-08-30 | 2006-12-13 | Method for barrier interface preparation of copper interconnect |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150132946A1 true US20150132946A1 (en) | 2015-05-14 |
Family
ID=39136456
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/639,050 Active 2029-02-04 US8916232B2 (en) | 2006-08-30 | 2006-12-13 | Method for barrier interface preparation of copper interconnect |
US14/558,548 Abandoned US20150132946A1 (en) | 2006-08-30 | 2014-12-02 | Methods for barrier interface preparation of copper interconnect |
US14/558,554 Abandoned US20150128861A1 (en) | 2006-08-30 | 2014-12-02 | Apparatus for barrier interface preparation of copper interconnect |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/639,050 Active 2029-02-04 US8916232B2 (en) | 2006-08-30 | 2006-12-13 | Method for barrier interface preparation of copper interconnect |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/558,554 Abandoned US20150128861A1 (en) | 2006-08-30 | 2014-12-02 | Apparatus for barrier interface preparation of copper interconnect |
Country Status (7)
Country | Link |
---|---|
US (3) | US8916232B2 (en) |
JP (1) | JP5484053B2 (en) |
CN (1) | CN101511494B (en) |
MY (1) | MY157906A (en) |
SG (1) | SG174749A1 (en) |
TW (1) | TWI378533B (en) |
WO (1) | WO2008027214A2 (en) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090304914A1 (en) * | 2006-08-30 | 2009-12-10 | Lam Research Corporation | Self assembled monolayer for improving adhesion between copper and barrier layer |
JP4755573B2 (en) * | 2006-11-30 | 2011-08-24 | 東京応化工業株式会社 | Processing apparatus and processing method, and surface treatment jig |
JP4971078B2 (en) * | 2007-08-30 | 2012-07-11 | 東京応化工業株式会社 | Surface treatment equipment |
US8679970B2 (en) * | 2008-05-21 | 2014-03-25 | International Business Machines Corporation | Structure and process for conductive contact integration |
JP2010040771A (en) * | 2008-08-05 | 2010-02-18 | Rohm Co Ltd | Method of manufacturing semiconductor device |
EP2159304A1 (en) * | 2008-08-27 | 2010-03-03 | Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO | Apparatus and method for atomic layer deposition |
US9177917B2 (en) * | 2010-08-20 | 2015-11-03 | Micron Technology, Inc. | Semiconductor constructions |
JP5862353B2 (en) * | 2011-08-05 | 2016-02-16 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
US9312203B2 (en) | 2013-01-02 | 2016-04-12 | Globalfoundries Inc. | Dual damascene structure with liner |
US9865501B2 (en) * | 2013-03-06 | 2018-01-09 | Lam Research Corporation | Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer |
US8916469B2 (en) * | 2013-03-12 | 2014-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating copper damascene |
CN104517893A (en) * | 2013-09-29 | 2015-04-15 | 格罗方德半导体公司 | In-situ vapor deposition method for enabling self-assembled monolayer to form copper adhesion promoter and diffusion barrier |
US9269585B2 (en) * | 2014-01-10 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for cleaning metal gate surface |
US9490211B1 (en) * | 2015-06-23 | 2016-11-08 | Lam Research Corporation | Copper interconnect |
KR102059324B1 (en) * | 2016-05-16 | 2019-12-26 | 가부시키가이샤 아루박 | Formation method of Cu film |
US9768063B1 (en) | 2016-06-30 | 2017-09-19 | Lam Research Corporation | Dual damascene fill |
US9875958B1 (en) | 2016-11-09 | 2018-01-23 | International Business Machines Corporation | Trace/via hybrid structure and method of manufacture |
US10731250B2 (en) * | 2017-06-06 | 2020-08-04 | Lam Research Corporation | Depositing ruthenium layers in interconnect metallization |
TWI810808B (en) * | 2017-12-22 | 2023-08-01 | 美商應用材料股份有限公司 | Methods for depositing blocking layers on conductive surfaces |
US10801978B2 (en) * | 2018-03-12 | 2020-10-13 | Nova Measuring Instruments, Inc. | XPS metrology for process control in selective deposition |
JP2019192892A (en) | 2018-04-18 | 2019-10-31 | 東京エレクトロン株式会社 | Processing system and processing method |
CN109273402B (en) * | 2018-09-13 | 2020-08-25 | 德淮半导体有限公司 | Manufacturing method of metal barrier layer, metal interconnection structure and manufacturing method thereof |
TW202117075A (en) * | 2019-09-25 | 2021-05-01 | 日商東京威力科創股份有限公司 | Substrate liquid treatment method and substrate liquid treatment device |
US11410881B2 (en) | 2020-06-28 | 2022-08-09 | Applied Materials, Inc. | Impurity removal in doped ALD tantalum nitride |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6017820A (en) * | 1998-07-17 | 2000-01-25 | Cutek Research, Inc. | Integrated vacuum and plating cluster system |
US20020142590A1 (en) * | 2001-03-28 | 2002-10-03 | Wei Pan | Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics |
US20030143837A1 (en) * | 2002-01-28 | 2003-07-31 | Applied Materials, Inc. | Method of depositing a catalytic layer |
US20050009325A1 (en) * | 2003-06-18 | 2005-01-13 | Hua Chung | Atomic layer deposition of barrier materials |
US20050064708A1 (en) * | 2003-03-26 | 2005-03-24 | May Charles E. | Via and metal line interface capable of reducing the incidence of electro-migration induced voids |
US20050106865A1 (en) * | 2001-09-26 | 2005-05-19 | Applied Materials, Inc. | Integration of ALD tantalum nitride for copper metallization |
US20060251800A1 (en) * | 2005-03-18 | 2006-11-09 | Weidman Timothy W | Contact metallization scheme using a barrier layer over a silicide layer |
US20070040275A1 (en) * | 2005-08-12 | 2007-02-22 | Lee Han C | Semiconductor device including diffusion barrier and method for manufacturing the same |
US20070098902A1 (en) * | 2005-06-17 | 2007-05-03 | Cornell Research Foundation, Inc. | Fabricating inorganic-on-organic interfaces for molecular electronics employing a titanium coordination complex and thiophene self-assembled monolayers |
US20070099422A1 (en) * | 2005-10-28 | 2007-05-03 | Kapila Wijekoon | Process for electroless copper deposition |
US20070099420A1 (en) * | 2005-11-02 | 2007-05-03 | Dominguez Juan E | Direct tailoring of the composition and density of ALD films |
US20070108063A1 (en) * | 2005-09-28 | 2007-05-17 | Ebara Corporation | Layer forming method, layer forming apparatus, workpiece processing apparatus, interconnect forming method, and substrate interconnect structure |
US20070292603A1 (en) * | 2005-08-31 | 2007-12-20 | Lam Research Corporation | Processes and systems for engineering a barrier surface for copper deposition |
US20090304914A1 (en) * | 2006-08-30 | 2009-12-10 | Lam Research Corporation | Self assembled monolayer for improving adhesion between copper and barrier layer |
US7902064B1 (en) * | 2007-05-16 | 2011-03-08 | Intermolecular, Inc. | Method of forming a layer to enhance ALD nucleation on a substrate |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6362099B1 (en) | 1999-03-09 | 2002-03-26 | Applied Materials, Inc. | Method for enhancing the adhesion of copper deposited by chemical vapor deposition |
JP2001015517A (en) | 1999-07-02 | 2001-01-19 | Ebara Corp | Semiconductor device and its manufacture |
US6413858B1 (en) * | 1999-08-27 | 2002-07-02 | Micron Technology, Inc. | Barrier and electroplating seed layer |
JP4537523B2 (en) | 2000-02-16 | 2010-09-01 | 富士通株式会社 | Pulse plating method for Cu-based embedded wiring |
US7135404B2 (en) * | 2002-01-10 | 2006-11-14 | Semitool, Inc. | Method for applying metal features onto barrier layers using electrochemical deposition |
US6921712B2 (en) * | 2000-05-15 | 2005-07-26 | Asm International Nv | Process for producing integrated circuits including reduction using gaseous organic compounds |
JP4169950B2 (en) | 2001-05-18 | 2008-10-22 | Necエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US6528884B1 (en) | 2001-06-01 | 2003-03-04 | Advanced Micro Devices, Inc. | Conformal atomic liner layer in an integrated circuit interconnect |
US6686278B2 (en) * | 2001-06-19 | 2004-02-03 | United Microelectronics Corp. | Method for forming a plug metal layer |
JP2003059861A (en) | 2001-08-09 | 2003-02-28 | Tokyo Electron Ltd | Method and device for forming film |
KR100805843B1 (en) | 2001-12-28 | 2008-02-21 | 에이에스엠지니텍코리아 주식회사 | Method of forming copper interconnection, semiconductor device fabricated by the same and system for forming copper interconnection |
US20040040504A1 (en) * | 2002-08-01 | 2004-03-04 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing apparatus |
US20050079703A1 (en) * | 2003-10-09 | 2005-04-14 | Applied Materials, Inc. | Method for planarizing an interconnect structure |
US7527826B2 (en) * | 2004-04-14 | 2009-05-05 | University Of Massachusetts | Adhesion of a metal layer to a substrate by utilizing an organic acid material |
US7211509B1 (en) * | 2004-06-14 | 2007-05-01 | Novellus Systems, Inc, | Method for enhancing the nucleation and morphology of ruthenium films on dielectric substrates using amine containing compounds |
DE102004037089A1 (en) * | 2004-07-30 | 2006-03-16 | Advanced Micro Devices, Inc., Sunnyvale | A technique for making a passivation layer prior to depositing a barrier layer in a copper metallization layer |
US7476618B2 (en) | 2004-10-26 | 2009-01-13 | Asm Japan K.K. | Selective formation of metal layers in an integrated circuit |
WO2006058034A2 (en) * | 2004-11-22 | 2006-06-01 | Intermolecular, Inc. | Molecular self-assembly in substrate processing |
US20060240187A1 (en) * | 2005-01-27 | 2006-10-26 | Applied Materials, Inc. | Deposition of an intermediate catalytic layer on a barrier layer for copper metallization |
US7459392B2 (en) * | 2005-03-31 | 2008-12-02 | Intel Corporation | Noble metal barrier and seed layer for semiconductors |
US20070281476A1 (en) * | 2006-06-02 | 2007-12-06 | Lavoie Adrien R | Methods for forming thin copper films and structures formed thereby |
-
2006
- 2006-12-13 US US11/639,050 patent/US8916232B2/en active Active
-
2007
- 2007-08-17 WO PCT/US2007/018250 patent/WO2008027214A2/en active Application Filing
- 2007-08-17 CN CN2007800325321A patent/CN101511494B/en not_active Expired - Fee Related
- 2007-08-17 SG SG2011062163A patent/SG174749A1/en unknown
- 2007-08-17 MY MYPI20090659A patent/MY157906A/en unknown
- 2007-08-17 JP JP2009526620A patent/JP5484053B2/en not_active Expired - Fee Related
- 2007-08-29 TW TW096131988A patent/TWI378533B/en not_active IP Right Cessation
-
2014
- 2014-12-02 US US14/558,548 patent/US20150132946A1/en not_active Abandoned
- 2014-12-02 US US14/558,554 patent/US20150128861A1/en not_active Abandoned
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6017820A (en) * | 1998-07-17 | 2000-01-25 | Cutek Research, Inc. | Integrated vacuum and plating cluster system |
US20020142590A1 (en) * | 2001-03-28 | 2002-10-03 | Wei Pan | Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics |
US20050106865A1 (en) * | 2001-09-26 | 2005-05-19 | Applied Materials, Inc. | Integration of ALD tantalum nitride for copper metallization |
US20030143837A1 (en) * | 2002-01-28 | 2003-07-31 | Applied Materials, Inc. | Method of depositing a catalytic layer |
US20050064708A1 (en) * | 2003-03-26 | 2005-03-24 | May Charles E. | Via and metal line interface capable of reducing the incidence of electro-migration induced voids |
US20050009325A1 (en) * | 2003-06-18 | 2005-01-13 | Hua Chung | Atomic layer deposition of barrier materials |
US20060251800A1 (en) * | 2005-03-18 | 2006-11-09 | Weidman Timothy W | Contact metallization scheme using a barrier layer over a silicide layer |
US20070098902A1 (en) * | 2005-06-17 | 2007-05-03 | Cornell Research Foundation, Inc. | Fabricating inorganic-on-organic interfaces for molecular electronics employing a titanium coordination complex and thiophene self-assembled monolayers |
US20070040275A1 (en) * | 2005-08-12 | 2007-02-22 | Lee Han C | Semiconductor device including diffusion barrier and method for manufacturing the same |
US20070292603A1 (en) * | 2005-08-31 | 2007-12-20 | Lam Research Corporation | Processes and systems for engineering a barrier surface for copper deposition |
US20070108063A1 (en) * | 2005-09-28 | 2007-05-17 | Ebara Corporation | Layer forming method, layer forming apparatus, workpiece processing apparatus, interconnect forming method, and substrate interconnect structure |
US20070099422A1 (en) * | 2005-10-28 | 2007-05-03 | Kapila Wijekoon | Process for electroless copper deposition |
US20070099420A1 (en) * | 2005-11-02 | 2007-05-03 | Dominguez Juan E | Direct tailoring of the composition and density of ALD films |
US20090304914A1 (en) * | 2006-08-30 | 2009-12-10 | Lam Research Corporation | Self assembled monolayer for improving adhesion between copper and barrier layer |
US7902064B1 (en) * | 2007-05-16 | 2011-03-08 | Intermolecular, Inc. | Method of forming a layer to enhance ALD nucleation on a substrate |
Also Published As
Publication number | Publication date |
---|---|
US20080057198A1 (en) | 2008-03-06 |
US8916232B2 (en) | 2014-12-23 |
WO2008027214A2 (en) | 2008-03-06 |
CN101511494B (en) | 2013-01-30 |
US20150128861A1 (en) | 2015-05-14 |
WO2008027214A3 (en) | 2008-11-13 |
TWI378533B (en) | 2012-12-01 |
SG174749A1 (en) | 2011-10-28 |
MY157906A (en) | 2016-08-15 |
TW200832613A (en) | 2008-08-01 |
CN101511494A (en) | 2009-08-19 |
JP5484053B2 (en) | 2014-05-07 |
JP2010503204A (en) | 2010-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8916232B2 (en) | Method for barrier interface preparation of copper interconnect | |
US8241701B2 (en) | Processes and systems for engineering a barrier surface for copper deposition | |
US8771804B2 (en) | Processes and systems for engineering a copper surface for selective metal deposition | |
KR101423349B1 (en) | Self assembled monolayer for improving adhesion between copper and barrier layer | |
US8747960B2 (en) | Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide | |
KR100516337B1 (en) | Semiconductor device and manufacturing method thereof | |
JP5489717B2 (en) | Method and integrated system for conditioning a substrate surface for metal deposition | |
US8133812B2 (en) | Methods and systems for barrier layer surface passivation | |
US8053355B2 (en) | Methods and systems for low interfacial oxide contact between barrier and copper metallization | |
KR101506352B1 (en) | Processes and integrated systems for engineering a substrate surface for metal deposition | |
US10879114B1 (en) | Conductive fill | |
KR101487564B1 (en) | Methods and apparatus for barrier interface preparation of copper interconnect | |
US6784093B1 (en) | Copper surface passivation during semiconductor manufacturing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |