CN104517893A - In-situ vapor deposition method for enabling self-assembled monolayer to form copper adhesion promoter and diffusion barrier - Google Patents
In-situ vapor deposition method for enabling self-assembled monolayer to form copper adhesion promoter and diffusion barrier Download PDFInfo
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- CN104517893A CN104517893A CN201310455370.XA CN201310455370A CN104517893A CN 104517893 A CN104517893 A CN 104517893A CN 201310455370 A CN201310455370 A CN 201310455370A CN 104517893 A CN104517893 A CN 104517893A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract
The invention relates to an in-situ vapor deposition method for enabling a self-assembled monolayer to form a copper adhesion promoter and a diffusion barrier. The method includes the following steps that: a copper region is formed in a dielectric layer; a diffusion barrier containing a self-assembled monolayer is deposited on the copper region; and a covering layer is deposited on the self-assembled monolayer. In some embodiments, the covering layer and the self-assembled monolayer are deposited in the same treatment room.
Description
Technical field
The present invention relates generally to semiconductor applications, and the method for more espespecially self-assembled monolayer (self-assembled monolayer) original position (in-situ) vapour deposition.
Background technology
Along with the reduction of integrated circuit (IC) apparatus scales is to reach the higher productivity of higher frequency of operation, lower power consumption and entirety, manufactures interconnection reliably and manufacture and usefulness two aspect are becomed increasingly difficult.
In order to manufacture the reliable apparatus with fast service speed, copper (Cu) is because it has compared with low resistance compared to aluminium and more not easily produces electron transfer and stress migration and just becoming the material selecting to be formed interconnection line.
But Cu has various shortcoming.Such as, Cu is to SiO
2and the adhesion strength of other dielectric material is poor.Therefore, reliable diffusion barrier part and adhesion promoter is needed can to realize to make copper-connection.Some current used interface barrier layer materials comprises tantalum (Ta), tantalum nitride (TaN) and titanium (TiN).These layers are difficult to when depositing by prior art method be formed as even and continuous print layer part.This when the layer part thickness that will be deposited is less than 10 nanometer and these layer of part formed as through hole (via) as when being high-aspect-ratio (aspect ratio) (such as, depth ratio width) feature especially true.Known Cu/ cover layer interface can facilitate electron transfer (EM) fault, therefore optimizes Cu/ covering interface (cap interface) and has key for EM reliability usefulness.Therefore, the modified form method had for the formation of copper adhesion promoter and diffusion barrier part is expected.
Summary of the invention
Generally speaking, specific embodiments of the invention are provided for the method for self-assembled monolayer original position vapour deposition as copper adhesion promoter and diffusion barrier part.Copper region is formed in the dielectric layer.The diffusion barrier part be made up of self-assembled monolayer is deposited on copper overlying regions.Cap layer deposition is above self-assembled monolayer.In some specific embodiment, cover layer and self-assembled monolayer are deposited in identical process chamber.Specific embodiments of the invention can provide as reduced undesirable copper zone oxidation risk during fabrication schedule compared to the barrier layer materials of prior art, reduce waste of material and improve the advantages such as the adherence of barrier layer between copper region and cover layer and validity.
An aspect of the present invention comprises the method forming semiconductor structure.This method comprises and forms through hole in the dielectric layer; Form the first barrier layer in through-holes; Form copper region in through-holes; The second barrier layer is deposited at copper overlying regions; And at the second barrier layer disposed thereon cover layer.Deposit the second barrier layer to be included in chemical vapor deposition tool room and to deposit self-assembled monolayer.
Another aspect of the present invention comprises the method forming semiconductor structure.This method comprises and forms through hole in the dielectric layer; Form the first barrier layer in through-holes; Form copper region in through-holes; The second barrier layer is deposited at copper overlying regions; And at the second barrier layer disposed thereon cover layer.Deposit the second barrier layer to be included in atomic layer deposition tool room and to deposit self-assembled monolayer.
Another aspect of the present invention comprises the method forming semiconductor structure.This method comprises and forms through hole in the dielectric layer; Form the first barrier layer in through-holes; Form copper region in through-holes; The second barrier layer is deposited at copper overlying regions; And at the second barrier layer disposed thereon cover layer.Deposit the second barrier layer to be included in plasma enhanced chemical vapor deposition toolroom and to deposit self-assembled monolayer.
Accompanying drawing explanation
Collocation accompanying drawing will be able to understand these and other feature of the present invention more easily via the hereafter detailed description of the various aspect of the present invention, wherein:
Fig. 1 represents that the present invention one specific embodiment is in the semiconductor structure of starting point (starting point);
Fig. 2 represents the semiconductor structure after the subsequent processing steps forming through hole according to descriptive specific embodiment;
Fig. 3 represents the semiconductor structure after the subsequent processing steps of formation first barrier layer according to descriptive specific embodiment;
Fig. 4 represents the semiconductor structure after the subsequent processing steps forming copper region according to descriptive specific embodiment;
Fig. 5 represents the semiconductor structure after the subsequent processing steps of formation second barrier layer according to descriptive specific embodiment;
Fig. 6 represents the semiconductor structure after forming tectal subsequent processing steps according to descriptive specific embodiment;
Fig. 7 represents flow chart according to descriptive specific embodiment; And
Fig. 8 represents a part for the deposition tool for implementing descriptive specific embodiment.
Graphic may not according to ratio.Graphic only for statement, purpose does not lie in describes special parameter of the present invention.Graphic with being intended to only describe general specific embodiment of the present invention, and thus should be considered as the restriction in category.In the drawings, the element numbers matched represents the assembly matched.
Symbol description
100 semiconductor structures
102 dielectric layers
104 through holes
106 first barrier layers
108 bronze medal regions
110 second barrier layers, SAM layer
112 cover layers
200 semiconductor structures
300 semiconductor structures
400 semiconductor structures
500 semiconductor structures
600 semiconductor structures
700 flow charts
750,752,754,756,758 program steps
800 deposition tools
870 process chambers
872 wafers
874 pedestals
876 air intakes
878 adjuster valves.
Embodiment
Now with reference to accompanying drawing at more completely illustrated example specific embodiment herein, wherein represented is Illustrative embodiments.Illustrative embodiments of the present invention provides and uses original position gas phase deposition technology for depositing the method for self-assembled monolayer (SAM) film (film).In some specific embodiment, form SAM film in copper overlying regions, and in identical process chamber, above SAM film, form cover layer successively.The risk of undesired copper oxidation during this is reduced in fabrication schedule.In addition, strong cohesiveness mouth bond (interfacial bonding) curable Cu, and the Cu ion reducing that Cu injects ILD interface, thus reduce the risk of time dependence dielectric medium collapse (TDDB).
By understand this announcements available many multi-form embodied and should be inferred as be limited to the Illustrative embodiments carried of this paper.On the contrary, these specific embodiments through provide to such an extent as to this announcement by thorough and complete, and category of the present invention for reception and registration is given those skilled in the art.The object of term used herein is only special specific embodiment is described and is intended to not lie in limit this announcement.Such as, as used herein, singulative " ", " one ", " one " and " being somebody's turn to do " with being intended to comprise plural form, except context refers else simultaneously.Further, " one ", " one ", " one " etc. do not indicate restricted number with word, but instruction exists at least one quoted project.What will be further understood that is, " include " with word and/or " comprising " or, " comprising " and/or " including " in the existence for specifying described feature, region, complete thing (integer), step, operation, assembly and/or element during this specification, and the existence of one or more other its feature of non-excluded, region, complete thing, step, operation, assembly, element and/or group or increase.
The full section of this specification means described in conjunction with specific embodiments specific characteristic, structure or characteristic for " specific embodiment ", " specific embodiment ", " specific embodiment ", " Illustrative embodiments " or similar term and includes at least one specific embodiment of the present invention.Therefore, the word of the full section of this specification performance " in one embodiment ", " at a specific embodiment ", " at specific embodiment " and similar term can, but not necessarily to want, all mean identical specific embodiment.
" above cover " with word or " atop ", " be placed in ... on " or " being above placed in ", " underliing ", " in below " or " under " mean as the first structure, such as ground floor, the first assembly appear at as the second structure, the such as second layer, the second assembly on, wherein, as interface structure, such as interface layer, intermediary component (intervening element) can appear between the first assembly and the second assembly.
Referring again to icon, Fig. 1 represents that the present invention one specific embodiment is in the semiconductor structure 100 of starting point.Semiconductor structure 100 comprises dielectric layer 102.Dielectric layer 102 can be interlayer dielectric layer (interlevel dielectric layer, ILD).ILD can comprise multiple dielectric layer and comprise one or more etch stop with selection of land.
Fig. 2 represents the semiconductor structure 200 after the subsequent processing steps forming through hole 104 in dielectric layer 102.Industrywide standard can be used to etch and micro-shadow technology formation through hole.
Fig. 3 represents the semiconductor structure 300 after the subsequent processing steps forming the first barrier layer 106 in through hole 104 interior surface.First barrier layer can be metal level, as the layer part based on tantalum.First barrier layer is by being formed including, but not limited to any applicable deposition processs such as physical vapour deposition (PVD) (PVD), chemical vapour deposition (CVD) (CVD), plasma enhanced chemical vapor deposition (PECVD) or alds (ALD).
Fig. 4 represents the semiconductor structure 400 after the subsequent processing steps forming copper region 108, filling vias (104 of contrast Fig. 3).By forming copper region 108 including, but not limited to any applicable deposition processs such as plating.Behind deposited copper region 108, Cu is with stable crystal structure in annealing, and can then carry out if the leveling programs such as chemical gaseous phase polishing (CMP) are to make copper region 108 and the first barrier layer 106 and dielectric layer 102 in plane.
Fig. 5 represents the semiconductor structure 500 after the subsequent processing steps of formation second barrier layer 110.Second barrier layer is self-assembled monolayer (SAM), and is deposited via original position gas phase deposition technology.In one embodiment, SAM layer 110 amasss instrument via chemical gaseous phase and is deposited.In another specific embodiment, SAM layer 110 is deposited via plasma enhanced chemical vapor deposition instrument.In a particular embodiment, SAM layer 110 has scope from about 10 dusts to the thickness T of about 30 dusts.Specific embodiments of the invention can utilize various SAM, including, but not limited to amino silane (amino-silane), hydrosulphonyl silane (mercapto-silane), have the organosilan (organosilane with aromatic ring) of aromatic rings.
Spendable some amino silane SAM comprises:
APTMS：H2NCH2CH2CH2Si(OCH3)3；
APTES：H2NCH2CH2CH2Si(OC2H5)3；
APDMS:(3-aminopropyl) dimethylethoxysilane
(3-aminopropyldimethylethoxysilane)；
N-(2-aminoethyl)-3-aminopropyl trimethoxy silane
(EDA)(N-(2-aminoethyl)-3-aminopropyltrimethoxysilane)；
(3-dimethoxysilyl propyl group) diethylene three ammonia
(DETA)((3-trimethoxysilylpropyl)diethylenetriamine)；
4-aminophenyl trimethoxy silane (4-aminophenyltrimethoxysilane); And
Phenylamino-methyl trimethoxy silane
(phenylamino-methyltrimethoxysilane)。
Spendable some hydrosulphonyl silane SAM comprises:
MPTMS:3-mercaptopropyi trimethoxy silane
(3-mercaptopropyltrimethoxysilane)：HS(CH2)3Si(OCH3)3；
MPTES:3-mercaptopropyi three ethoxy silane
(3-mercaptopropyltriethoxysilane): HS (CH2) 3Si (OC2H5) 3; And MPMDMS:3-mercaptopropyi methyl dimethoxysilane
(3-mercaptopropylmethyldimethoxysilane)：
HS(CH2)3Si(CH3)(OCH3)2。
The organosilan with aromatic rings can comprise (CH2) n-Si (OCH3) 3.
Deposition parameter can comprise scope be 50 degree to 120 degree approximately Celsius approximately Celsius reaction temperature, scope from about 0.1 holder to the silane precursor vapour pressures of about 10 holders and scope from reaction time of about 1 minute to about 30 minutes.
Fig. 6 represents the semiconductor structure 600 after the subsequent processing steps forming cover layer 112.In a particular embodiment, cover layer 112 can comprise the nitride of silicon carbide or silicon carbide.In a particular embodiment, cover layer 112 can give depositing in identical room body as the second barrier layer 110.This provides because its limit copper region 108 is exposed to surrounding air the advantage preventing from copper region 108 being formed oxide.Other advantage can comprise minimizing and produces contaminated waste liquid and dimerization product and be effectively coated with high aspect ratio structure.In other specific embodiment, the first Room body can be used for deposition second barrier layer 110 and the second Room body can be used for sedimentary cover 112.Transfer chamber is used between first and second room body and carries wafer (wafer).In these specific embodiments, the second barrier layer 110 can be deposited from ald (ALD) room or plasma enhanced ALD (PEALD) room.
Fig. 7 represents flow chart 700 according to descriptive specific embodiment.In program step 750, form through hole (referring to 104 of Fig. 2).In program step 752, form the first barrier district (referring to 106 of Fig. 3).At some specific embodiment, the first barrier district can be metal or metallic compound, as tantalum or the compound based on tantalum.In other specific embodiment, the first barrier district can comprise self-assembled monolayer.In some specific embodiment, the first barrier district can be the material with the second barrier district with same material.In program step 754, form copper region (referring to 108 of Fig. 5).In program step 756, form the second barrier district (referring to 110 of Fig. 5).Second barrier district is self-assembled monolayer, and uses the instrument as chemical vapour deposition (CVD) (CVD) instrument, plasma enhanced chemical vapor deposition (PECVD) instrument, ALD instrument or PEALD instrument and so on to be deposited via original position vapour deposition.In program step 758, sedimentary cover 112(refers to 112 of Fig. 6).In a particular embodiment, cover layer 112 can comprise the nitride of silicon carbide or carbide.In a particular embodiment, can as the second barrier layer 110 sedimentary cover 112 in identical chamber body in subsequent processing steps.Therefore, semiconductor structure (such as wafer) need not be made between deposition second barrier layer 110 and sedimentary cover 112 to leave room body and can deposit both the second barrier layer 110 and cover layer 112 on semiconductor structure.
Fig. 8 represents a part for the deposition tool 800 for implementing descriptive specific embodiment.Deposition tool 800 comprises process chamber 870.In room body 870, deposition is the wafer 872 supported by pedestal 874.Reacting gas is applied equably via air intake 876 pairs of wafers 872.Via the pressure in adjuster valve 878 control treatment room 870.By depositing both the second barrier layer 110 and cover layer 112 in room body 870, being alleviated undesirable problem of oxidation (referring to Fig. 6) on copper region 108, thus being able to improved semiconductor fabrication schedule.
In each specific embodiment, can provide and configure design tool to produce the data collection for patterning semiconductor layer as described herein.Such as, data collection can be produced to produce the light shield in order to patterning structure layer as described herein part during micro-shadow operates.These design tools can comprise the set of one or more module and also can comprise hardware, software or its combination.Therefore, for example, instrument can be one or more software module, hardware module, software/hardware module or any set that it combines or arranges.In another embodiment, instrument to can be on it executive software or hardware implementing in calculation element wherein or other utensil.As used herein, module may utilize hardware, software or its any form combined to be achieved.Such as, one or more processor, controller, Application Specific Integrated Circuit (ASIC), programmable logic array (PLA), logic element, software program or other mechanism may be realized with comprising modules.In the implementation, various module as herein described may be achieved into discrete block or function and illustrated feature partly or entirely can be shared between one or more module.In other words, for the described field person that has ordinary skill after this explanations of reading by obviously known, various feature as herein described and function can be achieved and can be achieved with various combination and arrangement in one or more separation or sharing module in any given application.Even if the various feature of function or assembly can illustrate separately or advocate as separation module, described field has ordinary skill person will understand can between one or more common software and hardware assembly these features of sharing functionality, and this explanation must not need or imply that the hardware or component software that are separated are for realizing these feature or functions.
Obviously learn the method being provided for the vapour deposition of self-assembled monolayer original position.Although arranged in pairs or groups, Illustrative embodiments represents especially and the present invention is described, will understand those skilled in the art and will expect change and improve.Such as, although descriptive specific embodiment is illustrated as series of actions or event herein, understanding the present invention is not limited to order shown in these actions or event, unless there are clearly stating.According to the present invention, shown in some action can be different from herein and/or described with other action or event with different order and/or occur simultaneously.In addition, not all described step all can be used to implement a methodology in accordance with the present invention.In addition, can associate herein according to method of the present invention shown in formation and/or the process of described structure and associate other structure do not shown and be achieved.Therefore, the improving with being intended to contain all these fallen within true spirit of the present invention and changing of appended claims is appreciated that.
Claims (20)
1. form a method for semiconductor structure, it comprises:
Form through hole in the dielectric layer;
The first barrier layer is formed in this through hole;
Copper region is formed in this through hole;
The second barrier layer is deposited at this copper overlying regions; And
At this second barrier layer disposed thereon cover layer;
Wherein, deposit this second barrier layer to be included in chemical vapor deposition tool room and to deposit self-assembled monolayer.
2. method according to claim 1, wherein, is carried out in this chemical vapor deposition tool room at this this cover layer of the second barrier layer disposed thereon.
3. method according to claim 1, wherein, comprises depositing silicon carbide at this this cover layer of the second barrier layer disposed thereon.
4. method according to claim 1, wherein, deposits this self-assembled monolayer and comprises deposition amino silane.
5. method according to claim 4, wherein, deposits this amino silane and comprises deposition H2NCH2CH2CH2Si (OCH3) 3.
6. method according to claim 4, wherein, deposits this amino silane and comprises deposition H2NCH2CH2CH2Si (OC2H5) 3.
7. method according to claim 4, wherein, deposits this amino silane and comprises deposition (3-aminopropyl) dimethylethoxysilane.
8. method according to claim 4, wherein, deposits this amino silane and comprises deposition N-(2-aminoethyl)-3-aminopropyl trimethoxy silane.
9. method according to claim 4, wherein, deposits this amino silane and comprises deposition (3-dimethoxysilyl propyl group) diethylene three ammonia.
10. method according to claim 4, wherein, deposits this amino silane and comprises deposition 4-aminophenyl trimethoxy silane.
11. methods according to claim 4, wherein, deposit this amino silane and comprise deposition phenylamino-methyl trimethoxy silane.
12. methods according to claim 1, wherein, deposit this self-assembled monolayer and comprise deposition hydrosulphonyl silane.
13. methods according to claim 12, wherein, deposit this hydrosulphonyl silane and comprise deposition 3-mercaptopropyi trimethoxy silane.
14. methods according to claim 12, wherein, deposit this hydrosulphonyl silane and comprise deposition 3-mercaptopropyi three ethoxy silane.
15. methods according to claim 12, wherein, deposit this hydrosulphonyl silane and comprise deposition 3-mercaptopropyi methyl dimethoxysilane.
16. methods according to claim 1, wherein, deposit this self-assembled monolayer and comprise deposition organosilan.
17. methods according to claim 1, wherein, this first barrier layer is made up of the material having same material with this second barrier layer.
18. 1 kinds of methods forming semiconductor structure, it comprises:
Form through hole in the dielectric layer;
The first barrier layer is formed in this through hole;
Copper region is formed in this through hole;
The second barrier layer is deposited at this copper overlying regions; And
At this second barrier layer disposed thereon cover layer;
Wherein, deposit this second barrier layer to be included in atomic layer deposition tool room and to deposit self-assembled monolayer.
19. 1 kinds of methods forming semiconductor structure, it comprises:
Form through hole in the dielectric layer;
The first barrier layer is formed in this through hole;
Copper region is formed in this through hole;
The second barrier layer is deposited at this copper overlying regions; And
At this second barrier layer disposed thereon cover layer;
Wherein, deposit this second barrier layer to be included in plasma enhanced chemical vapor deposition toolroom and to deposit self-assembled monolayer.
20. methods according to claim 19, wherein, are carried out in this plasma enhanced chemical vapor deposition toolroom at this second barrier layer disposed thereon cover layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910627579.7A CN110391177A (en) | 2013-09-29 | 2013-09-29 | The method that self-assembled monolayer is vapor-deposited as copper adhesion promoter and diffusion barrier part in situ |
| CN201310455370.XA CN104517893A (en) | 2013-09-29 | 2013-09-29 | In-situ vapor deposition method for enabling self-assembled monolayer to form copper adhesion promoter and diffusion barrier |
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| Publication number | Publication date |
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| CN110391177A (en) | 2019-10-29 |
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Application publication date: 20150415 |