CN101197312A - Method for forming double mosaic structure - Google Patents
Method for forming double mosaic structure Download PDFInfo
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- CN101197312A CN101197312A CNA2006101191533A CN200610119153A CN101197312A CN 101197312 A CN101197312 A CN 101197312A CN A2006101191533 A CNA2006101191533 A CN A2006101191533A CN 200610119153 A CN200610119153 A CN 200610119153A CN 101197312 A CN101197312 A CN 101197312A
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- damascene structure
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Abstract
A dual-damascene structure forming method comprises the following steps that: a semiconductor substrate is provided; a metal conductor layer is formed in the semiconductor substrate; a nitrous high stress medium layer is formed on the semiconductor substrate; a dielectric layer is formed on the nitrous high stress medium layer; an opening is formed in the dielectric layer. In the device formed by the method, metal conducting wires along the medium layer have no problem of electric breakdown.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of dual-damascene structure.
Background technology
Along with reducing gradually of semiconductor technology live width, industry is selected the interconnection material of copper as back segment for use, and is corresponding, selects for use advanced low-k materials as insulating material.Because copper is difficult to etching and very easily diffusion, introduce dual-damascene technics, overcome the shortcoming that is difficult to etching, and the introducing barrier layer stops the diffusion of copper in advanced low-k materials, material as the barrier layer can be a metal material, for example, and titanium, titanium nitride etc., also can be dielectric material, silica etc. for example.Number of patent application is that 02106882.8 Chinese patent discloses a kind of dual-damascene technics.Fig. 1 to Fig. 4 is a manufacture method generalized section of stating disclosed dual-damascene technics.
As shown in Figure 1, provide a substrate 100 with metal carbonyl conducting layer, described metal carbonyl conducting layer material can be a copper.In described substrate 100, form first dielectric layer 102, described first dielectric layer 102 is used for covering the copper surface of the metal carbonyl conducting layer of substrate 100, to avoid described copper surface to be exposed in the air or in other aggressive chemistry processing procedure, the method of its formation is plasma enhanced chemical vapor deposition (PECVD), and its thickness is 30 to 100nm.
Form second dielectric layer 104 on described first dielectric layer 102, described second dielectric layer 104 is an advanced low-k materials.Form an anti-reflecting layer 106 on described second dielectric layer 104, described anti-reflecting layer 106 can be the organic or inorganic material.On described anti-reflecting layer 106, form a photoresist layer 108, form connecting hole patterns of openings 110 by exposure imaging.
As shown in Figure 2, with described photoresist layer 108 is the cover curtain, by etching described connecting hole patterns of openings 110 is transferred to formation connecting hole 110a in the described anti-reflecting layer 106 and second dielectric layer 104, described connecting hole 110a exposes described first dielectric layer 102 surfaces in the bottom.
Spin coating photoresist and form channel patterns in described connecting hole 110a and on the anti-reflecting layer 106 is transferred to described channel patterns in the described anti-reflecting layer 106 and second dielectric layer 104 by etching, forms groove 112 as shown in Figure 3.And remove described anti-reflecting layer 106.
As shown in Figure 4, remove first dielectric layer 102 of described connecting hole 110a bottom by etching.
In described groove 112 and connecting hole 110a the filled conductive material for example copper promptly form copper dual-damascene structure.
In the manufacturing process of above-mentioned dual-damascene structure, introducing material is cover layer and the etching stop layer of first dielectric layer 102 of silicon nitride as copper surface in the substrate.The reacting gas of the described silicon nitride of described formation is ammonia (NH
3), silane (SiH
4), because the another kind of product hydrogen of above-mentioned ammonia and silane reaction is bound in the silicon nitride film in a large number, the silicon nitride film characteristic of the generation that makes is degraded, breakdown characteristics descends.As shown in Figure 5, in described substrate 100, be formed with the first copper conductor 100a and the second copper conductor 100b, electric insulation between the described first copper conductor 100a and the second copper conductor 100b, in the manufacture process of device, introducing material is the cover layer of first dielectric layer 102 of silicon nitride work as the first copper conductor 100a and the second copper conductor 100b upper surface, to avoid the copper surface oxidized.When work, electrical breakdown can take place along described first dielectric layer 102 in the first copper conductor 100a and the second copper conductor 100b, has breakdown current 101 to flow through from described first dielectric layer 102, causes device electrically to fail behind the device that said structure forms.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of formation method of dual-damascene structure, to solve the problem that electrical breakdown takes place between the different metal lead in the existing dual-damascene structure.
For achieving the above object, the formation method of a kind of dual-damascene structure provided by the invention comprises:
The semiconductor substrate is provided, in the described semiconductor-based end, is formed with metal carbonyl conducting layer; On the described semiconductor-based end, form nitrogenous heavily stressed dielectric layer; On described heavily stressed dielectric layer, form dielectric layer; In described dielectric layer, form opening.
Described metal carbonyl conducting layer material comprises a kind of or its combination in copper, aluminium, titanium, titanium nitride, the tungsten.Described heavily stressed dielectric layer comprises a kind of or its combination in silicon nitride, carbon nitrogen silicon compound, the O-N-Si compound.
The formation method of described heavily stressed dielectric layer comprises a kind of in physical vapour deposition (PVD), plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, high density plasma CVD, the ald.
The reacting gas that forms described silicon nitride comprises silane and ammonia.The radio frequency source power that forms described silicon nitride is 800 to 960 watts.Described silane flow rate is 420 to 490sccm, and ammonia flow is 100 to 200sccm.The reacting gas that forms described silicon nitride comprises nitrogen, and the flow of nitrogen is 15000 to 20000sccm.The ambient pressure that forms described silicon nitride is 3 to 5 holders, and temperature is 300 to 600 ℃.
Described dielectric layer comprises a kind of or its combination in black diamond, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, silica, silicon nitride, the carborundum.
This method further comprises: fill metal material in described opening.
Compared with prior art, the present invention has the following advantages: the present invention is when forming dielectric layer, increase nitrogen in the reactant or contain the flow of nitrogen reactant, the content of nitrogen is higher in the feasible nitrogenous heavily stressed dielectric layer that generates, nitrogen helps to restrain carrier mobility in the described silicon nitride film layer, increase dielectric constant, reduce leakage current; Simultaneously, one of the product hydrogen of reaction can be driven out of from silicon nitride film layer, improve the puncture voltage of silicon nitride film layer by constraint nitrogen in silicon nitride film layer; Because hydrogen can make the rete characteristic degrade in silicon nitride film layer, reduce the internal stress of rete, reduce puncture voltage, thereby by fetter the hydrogen that nitrogen has reduced or eliminated reduction rete puncture voltage on the one hand in silicon nitride film layer, the content that improves silicon nitride film layer nitrogen simultaneously can further improve the puncture voltage of rete again.Thereby the voltage endurance capability and the stability of the device that forms have been improved.
Description of drawings
Fig. 1 to Fig. 4 is the manufacture method generalized section of existing a kind of dual-damascene technics;
The device that Fig. 5 makes for existing dual-damascene technics manufacture method produces the generalized section of electrical breakdown in dielectric layer;
Fig. 6 is the flow chart of dual-damascene structure manufacture method of the present invention;
Fig. 7 to Figure 16 is the dual-damascene structure manufacture method generalized section according to the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Because copper is diffusion and easily oxidized easily, need cover barrier material deposited copper after on metallic copper, expose externally in the environment to avoid copper that oxidized or copper is direct to be contacted with advanced low-k materials and spread to the open air.Simultaneously, described barrier material also can be used as the etching stop layer of making the lower interconnection structure, and described etching stop layer is retained in the device as the part of intermetallic dielectric layer.By in substrate, forming the barrier material of nitrogenous heavily stressed dielectric layer, improve the puncture voltage that forms device among the present invention, thereby improve the stability and the life-span of device with this as metallic copper with metal level.
Fig. 6 is the flow chart of dual-damascene structure manufacture method of the present invention.
As shown in Figure 6, at first, provide the semiconductor substrate, in the described semiconductor-based end, be formed with metal carbonyl conducting layer (S200).The described semiconductor-based end can be materials such as silicon on polysilicon, monocrystalline silicon, amorphous silicon, the insulating barrier (SOI), arsenicization are sowed, silicon Germanium compound, and described plain conductor layer material can be a kind of or its combination in copper, aluminium, titanium, titanium nitride, the tungsten.
On the described semiconductor-based end, form nitrogenous heavily stressed dielectric layer (S210).Described heavily stressed dielectric layer comprises a kind of or its combination in silicon nitride, carbon nitrogen silicon compound, the O-N-Si compound.The formation method of described heavily stressed dielectric layer is a kind of in physical vapour deposition (PVD), plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, high density plasma CVD, the ald.
On described nitrogenous heavily stressed dielectric layer, form dielectric layer (S220).Described dielectric layer is a kind of or its combination in black diamond, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, silica, silicon nitride, the carborundum.The method that forms described dielectric layer is a kind of or its combination in physical vapour deposition (PVD), the chemical vapour deposition (CVD).
Form opening in described dielectric layer, described opening is connecting hole and groove (S230).
Below in conjunction with embodiment double mosaic structure manufacture method of the present invention is described in detail.
Fig. 7 to Figure 16 is the manufacture method generalized section according to the embodiment of the invention.
As shown in Figure 7, provide semiconductor substrate 200, in the described semiconductor-based end 200, be formed with device layer and metal carbonyl conducting layer 200a, 200b.The described semiconductor-based end 200 can be materials such as silicon on polysilicon, monocrystalline silicon, amorphous silicon, the insulating barrier (SOI), arsenicization are sowed, silicon Germanium compound, and described device layer can be a metal oxide semiconductor transistor.Described metal carbonyl conducting layer 200a, 200b material can be a kind of or its combinations in copper, aluminium, titanium, titanium nitride, the tungsten.The 200a of metal carbonyl conducting layer described in the present embodiment, 200b material are copper.
As shown in Figure 8, at first, to carrying out the plasma surface preliminary treatment in the described semiconductor-based end 200 with device layer.Can reduce or eliminate the pollutant of substrate surface by the plasma surface preliminary treatment, improve the character of Facing material of the described semiconductor-based ends 200, strengthen the dielectric layer of subsequent technique formation and the adhesiveness on surface, the described semiconductor-based ends 200, simultaneously, can remove the cupric oxide on metal carbonyl conducting layer 200a, 200b surface by ammonia plasmas.Select for use ammonia as forming isoionic source gas in the present embodiment, feed assist gas nitrogen simultaneously.The process cavity of vacuum is sent at the described semiconductor-based end 200, and fed ammonia and nitrogen in chamber, open radio frequency source and be adjusted to suitable power, ammonia ionization under the effect of radio frequency source generates ammonia plasmas.Ammonia plasmas acts on surface, the described semiconductor-based ends 200 under the acceleration of electric field.Can be by the ammonia plasmas surface preparation with surface, the semiconductor-based ends 200 owing to be exposed to pollutant, the aqueous vapor removal that external environment condition absorbs, the adhesion between other rete that helps depositing in surface, the semiconductor-based ends 200 and the subsequent technique.Described ammonia plasmas radio frequency source power can be 100 to 500 watts, and the flow of ammonia is 100 to 200sccm.The time of ammonia plasmas surface preparation is 10 to 30s, and the vacuum degree of described process cavity is 3 to 6 holders.In the present embodiment, described ammonia plasmas radio frequency source power can be 300 watts, and the flow of ammonia is 160sccm.The time of ammonia plasmas surface preparation is 20s, and the vacuum degree of described process cavity is 4.2 holders.Nitrogen flow is 18000sccm.
After the plasma preliminary treatment of finishing surface, the described semiconductor-based ends 200, on surface, the described semiconductor-based ends 200, deposit a nitrogenous heavily stressed dielectric layer 202.The method that deposits described nitrogenous heavily stressed dielectric layer 202 is a kind of in physical vapour deposition (PVD), low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma CVD, the ald.The reacting gas of the heavily stressed dielectric layer 202 that described deposition is nitrogenous is a kind of or its combination in ammonia, silane, TEOS, dichloro-dihydro silicon, nitrous oxide, the nitrogen.Described nitrogenous heavily stressed dielectric layer 202 is a kind of or its combination in silicon nitride, nitrogen silicon oxide compound, the nitrogen-doped silicon carbide.Nitrogenous heavily stressed dielectric layer 202 thickness of described deposition are 20 to 80nm.
The deposition of described nitrogenous heavily stressed dielectric layer 202 can be carried out in same chamber (chamber) with aforementioned ammonia plasmas surface preparation, with described nitrogenous heavily stressed dielectric layer 202 is that silicon nitride is an example, after the ammonia plasmas surface treatment is finished at the described semiconductor-based end 200, the reacting gas that feed to generate nitrogenous heavily stressed dielectric layer 202 in process cavity is ammonia and silane for example, regulate the flow of silane and ammonia, feed nitrogen simultaneously as assist gas, make the silicon nitride film that generates have higher nitrogen content.In the present embodiment, the flow of described silane is that silane flow rate is 420 to 490sccm, and ammonia flow is 100 to 200sccm.The flow of nitrogen is 15000 to 20000sccm.The ambient pressure that forms described silicon nitride is 3 to 5 holders, and temperature is 300 to 600 ℃.Radio frequency source power is 800 to 960 watts, and the reaction time is about 10 to 30 seconds.
The detailed step that carries out described ammonia plasmas surface preparation and the described nitrogenous heavily stressed dielectric layer 202 of deposition in same chamber is as follows: open chamber, process cavity is sent at the described semiconductor-based end 200, regulating chamber temp is 400 ℃, and the pressure of environment is 3 to 5 holders; Feed ammonia and nitrogen in process cavity, the flow of described ammonia is 160sccm, and the flow of nitrogen is 18000sccm; Regulating radio frequency source power is 100 to 500 watts, and chamber temp remains unchanged, and keeping the flow of ammonia is 160sccm, and the flow of nitrogen body is 18000sccm.The pressure that keeps environment is 3 to 5 holders, and the ammonia plasmas surface-treated time is 10 to 30 seconds; In reaction chamber, feed silane, the flow of silane is 420 to 490sccm, keep the flow of ammonia and nitrogen constant, the holding chamber room temperature improves radio frequency source power and is 800 to 960W, described silane and ammonia gas react generate silicon nitride, because the flow of nitrogen is bigger in the course of reaction, unnecessary nitrogen partly is bound in the described silicon nitride film layer, and nitrogen helps to restrain carrier mobility in the described silicon nitride film layer, increase dielectric constant, reduce leakage current; Simultaneously, one of the product hydrogen of reaction can be driven out of from silicon nitride film layer, improve the puncture voltage of silicon nitride film layer by constraint nitrogen in silicon nitride film layer; Because hydrogen can make the rete characteristic degrade in silicon nitride film layer, reduce the internal stress of rete, and reduction puncture voltage, thereby by fetter the hydrogen that nitrogen has reduced or eliminated reduction rete puncture voltage on the one hand in silicon nitride film layer, the content that improves silicon nitride film layer nitrogen simultaneously can further improve the rete puncture voltage again.
As shown in Figure 9, on described nitrogenous heavily stressed dielectric layer 202, form dielectric layer 204.Described dielectric layer 204 is a kind of or its combination in black diamond, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, silica, silicon nitride, the carborundum.The method that forms described dielectric layer 204 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).Described dielectric layer 204 can be one or more layers.
After forming described dielectric layer 204, need form groove and connecting hole in described dielectric layer 204, the method that forms groove and connecting hole comprises: form connecting hole after going ahead of the rest into groove, form groove behind the formation connecting hole earlier.Present embodiment is that example describes to form earlier the situation that forms groove behind the connecting hole.
As shown in figure 10, spin coating anti-reflecting layer 206 on described dielectric layer 204, spin coating first photoresist layer 208 on described anti-reflecting layer 206 forms connecting hole pattern 210 by technologies such as exposure imagings.As shown in figure 11, be barrier material with described first photoresist layer 208, described anti-reflecting layer 206 of etching and dielectric layer 204 form connecting hole 210a in described dielectric layer 204, and described connecting hole 210a exposes described nitrogenous heavily stressed dielectric layer 202 surfaces in the bottom.
As shown in figure 12, remove described first photoresist layer 208 and anti-reflecting layer 206 by technologies such as ashing (Ashing), cleanings.As shown in figure 13, spin coating sacrifice layer 212 in described connecting hole 210a and on the dielectric layer 204, described sacrifice layer 212 can be photoresist, antireflection material etc.Spin coating second photoresist layer 214 on described sacrifice layer 212, and exposure imaging generates channel patterns 216.
As shown in figure 14, described channel patterns 216 is transferred to formation groove 216a on the described dielectric layer 204, remove described second photoresist layer 214 and sacrifice layer 212 by etching.As shown in figure 15, expose on nitrogenous heavily stressed dielectric layer 202 to described metal carbonyl conducting layer 200a, the 200b surface of the described connecting hole 210a of etching bottom.As shown in figure 16, in described connecting hole 210a and groove 216a, fill metal material, for example copper.By when forming rete 202, improving the content of nitrogen, reduce the content of hydrogen among the present invention, thereby the stress that has improved rete has improved the puncture voltage of rete.Further, the voltage endurance capability and the stability of the device that forms have been improved.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1. the formation method of a dual-damascene structure comprises:
The semiconductor substrate is provided, in the described semiconductor-based end, is formed with metal carbonyl conducting layer;
On the described semiconductor-based end, form nitrogenous heavily stressed dielectric layer;
On described heavily stressed dielectric layer, form dielectric layer;
In described dielectric layer, form opening.
2. the formation method of dual-damascene structure as claimed in claim 1, it is characterized in that: described metal carbonyl conducting layer material comprises a kind of or its combination in copper, aluminium, titanium, titanium nitride, the tungsten.
3. the formation method of dual-damascene structure as claimed in claim 1, it is characterized in that: described heavily stressed dielectric layer comprises a kind of or its combination in silicon nitride, carbon nitrogen silicon compound, the O-N-Si compound.
4. the formation method of dual-damascene structure as claimed in claim 1 is characterized in that: the formation method of described heavily stressed dielectric layer comprises a kind of in physical vapour deposition (PVD), plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, high density plasma CVD, the ald.
5. as the formation method of dual-damascene structure as described in the claim 3, it is characterized in that: the reacting gas that forms described silicon nitride comprises silane and ammonia.
6. the formation method of dual-damascene structure as claimed in claim 3, it is characterized in that: the radio frequency source power that forms described silicon nitride is 800 to 960 watts.
7. the formation method of dual-damascene structure as claimed in claim 5 is characterized in that: described silane flow rate is 420 to 490sccm, and ammonia flow is 100 to 200sccm.
8. the formation method of dual-damascene structure as claimed in claim 5, it is characterized in that: the reacting gas that forms described silicon nitride comprises nitrogen, the flow of nitrogen is 15000 to 20000sccm.
9. the formation method of dual-damascene structure as claimed in claim 5 is characterized in that: the ambient pressure that forms described silicon nitride is 3 to 5 holders, and temperature is 300 to 600 ℃.
10. the formation method of dual-damascene structure as claimed in claim 1, it is characterized in that: described dielectric layer comprises a kind of or its combination in black diamond, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, silica, silicon nitride, the carborundum.
11. the formation method of dual-damascene structure as claimed in claim 1 is characterized in that: this method further comprises: fill metal material in described opening.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446840A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for increasing breakdown voltage of double-Damascus structure dielectric barrier layer film |
| CN102446831A (en) * | 2011-09-29 | 2012-05-09 | 上海华力微电子有限公司 | Method for pretreating copper surface |
| CN110854131A (en) * | 2019-10-25 | 2020-02-28 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
-
2006
- 2006-12-05 CN CN200610119153A patent/CN100576496C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446831A (en) * | 2011-09-29 | 2012-05-09 | 上海华力微电子有限公司 | Method for pretreating copper surface |
| CN102446840A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for increasing breakdown voltage of double-Damascus structure dielectric barrier layer film |
| CN110854131A (en) * | 2019-10-25 | 2020-02-28 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
| US11380716B2 (en) | 2019-10-25 | 2022-07-05 | Tcl China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof |
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| CN100576496C (en) | 2009-12-30 |
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