JP2005266290A - 基板接合体の製造方法、基板接合体、及び電気光学装置 - Google Patents
基板接合体の製造方法、基板接合体、及び電気光学装置 Download PDFInfo
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- JP2005266290A JP2005266290A JP2004078284A JP2004078284A JP2005266290A JP 2005266290 A JP2005266290 A JP 2005266290A JP 2004078284 A JP2004078284 A JP 2004078284A JP 2004078284 A JP2004078284 A JP 2004078284A JP 2005266290 A JP2005266290 A JP 2005266290A
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Abstract
【解決手段】 配線基板3上にTFT13を実装して基板接合体2を製造する方法であって、配線基板3の電極パッド17とTFT13の電極パッド13aとを所定間隔で配置して、配線基板3およびTFT13を接着剤51により機械的に接続する工程と、配線基板3の電極パッド17および/またはTFT13の電極パッド13aからバンプ52を成長させて、配線基板3およびTFT13を電気的に接続する工程と、を有することを特徴とする。
【選択図】 図9
Description
更に、上記のバンプ105を形成する方法としては、メッキ法やスタッド等の工法が挙げられるが、ミクロンオーダーの微小エリアへのバンプ105の形成、タクト短縮、及び高さ均一性が優れるという観点からメッキ法が採用されることが多い。更に、このメッキ法の中でも電解メッキ法と無電解メッキ法があるが、下地電極やフォトリソ工程が不要になり、低コスト化及びタクト短縮が可能な方法として、無電解メッキ法を採用することが好ましい。
本発明の基板接合体の製造方法は、配線基板上に電気素子を実装して基板接合体を製造する方法であって、前記配線基板の電極パッドと前記電気素子の電極パッドとを所定間隔で配置して、前記配線基板および前記電気素子を機械的に接続する工程と、前記配線基板の電極パッドおよび/または前記電気素子の電極パッドからバンプを成長させて、前記配線基板および前記電気素子を電気的に接続する工程と、
を有することを特徴としている。
このようにすれば、基板の反りや段差によって電気素子と配線基板との接合位置が斜めになるように貼り合わせ精度が良くなく、電極パッド同士の間隔にバラツキが生じたとしても、これら電極パッド間にてバンプを十分に成長させることで、確実に電気的に接続させることができる。
これにより、接続のために加熱加圧量を高めて電気素子を破損、損傷させるような不具合なく、電気素子と配線基板との導通を確実に得ることができる。
このようにすれば、配線基板に対する電気素子の加熱加圧量がばらついても、両者の電極パッド同士を所定間隔で配置することができる。そして、電極パッド間においてバンプを成長させることにより、電極パッド同士を確実に電気的接続させることができる。
このように、電極パッドへ接着剤が濡れ広がらないようにしたので、電極パッド間において確実にバンプを成長させて電極パッド同士を電気的に接続させることができる。
このようにすれば、無電解メッキにより電極パッドに金属メッキを析出させバンプとして成長させることにより、電極パッド同士をバンプによって確実に電気的に接続させることができる。
このようにすれば、電極パッド間にて成長するバンプによる短絡が防止され、短絡による不具合を確実に防止することができる。
このようにすれば、成長させたバンプによって接続した電極パッド間の接続箇所を封止材料によって確実に保護することができ、接続の信頼性を高めることができる。
このようにすれば、基板の反りや段差によって電気素子と配線基板との接合位置が斜めになるように貼り合わせ精度が良くなく、電極パッド同士の間隔にバラツキが生じたとしても、これら電極パッド間にてバンプを十分に成長させることで、確実に電気的に接続させることができる。
これにより、接続のために加熱加圧量を高めて電気素子を破損、損傷させるような不具合なく、電気素子と配線基板との導通を確実に得ることができる。
このようにすれば、中央部分に接着剤を多く塗布して、転写時における電気素子の配線基板への高い密着性を確保することができる。
また、微小なエリアへの転写が難しい印刷法でも、大面積での接着剤の印刷が可能であり、しかも、接着剤による機械的接続部分の外周側の電極パッドを確実にメッキ液に接触させることができ、無電解メッキによる電気的接続を確実に行うことができる。
このようにすれば、互いに対向配置させた電極パッドにバンプを成長させて電気的に接続することにより、基板の反りや段差によって電気素子と配線基板との接合位置が斜めになるように貼り合わせ精度が良くなく、電極パッド同士の間隔にバラツキが生じたとしても、これら電極パッド間にてバンプを十分に成長させることで、確実に電気的に接続することができる。
これにより、接続のために加熱加圧量を高めて電気素子を破損、損傷させるような不具合なく、電気素子と配線基板との導通を確実に得ることができる。
ここで、図1は基板接合体及び電気光学装置の概略構成を示す断面図、図2から図14は基板接合体及び電気光学装置の製造工程を説明するための説明図、図15は配線基板を詳述するための断面拡大図、図16及び図17は本発明の配線基板を示す平面図である。
なお、以下の説明に用いる各図面では、各部材を認識可能な大きさとするため、各部材の縮尺を適宜変更している。
図1に示すように、電気光学装置1は、少なくとも基板接合体2を具備した構成となっている。当該基板接合体2は、配線基板3と、有機EL基板(発光素子基板)4とを後述の貼り合わせ及び転写工程によって接合された構成となっている。
配線基板3は、多層基板10と、多層基板10に形成された所定形状の配線パターン11と、配線パターン11に接続された回路部12と、有機EL素子24を駆動させるTFT(電気素子)13と、TFT13と配線パターン11とを接合するTFT接続部14と、有機EL素子24と配線パターン11とを接合する有機EL接続部15とによって構成されている。
ここで、TFT接続部14は、TFT13の端子パターンに応じて形成されるものであり、後述する無電解メッキ処理によって形成されるバンプ14aとから構成される。
更に、配線基板3と有機EL基板4との間には、封止ペースト30が充填されていると共に、有機EL接続部15及び陰極25間を電気的に導通させる導電性ペースト31が設けられている。
なお、本実施形態においては、発光素子基板として有機EL基板を採用した場合について説明するが、これに限定することなく、LED等の固体発光素子を有する発光素子基板を採用してもよい。
次に、図1に示す電気光学装置1及び基板接合体2の製造方法について図2から図9を参照して説明する。
まず、図2を参照し、TFT13を配線基板3に貼り合わせ及び転写させる前工程として、基礎基板40上にTFTを形成する工程について説明する。
なお、TFT13の製造方法は、高温プロセスを含む公知の技術が採用されるので、説明を省略し、基礎基板40と剥離層41について詳述する。
基礎基板40は、電気光学装置1の構成要素ではなく、TFT製造工程と、貼り合わせ及び転写工程にのみに用いられる部材である。具体的には、1000℃程度に耐える石英ガラス等の透光性耐熱基板が好ましい。また、石英ガラスの他、ソーダガラス、コーニング7059、日本電気ガラスOA−2等の耐熱性ガラス等が使用可能である。
この基礎基板の厚さには、大きな制限要素はないが、0.1mm〜0.5mm程度であることが好ましく、0.5mm〜1.5mm程度であることがより好ましい。基礎基板の厚さが薄すぎると強度の低下を招き、逆に厚すぎると基台の透過率が低い場合に照射光の減衰を招くからである。ただし、基台の照射光の透過率が高い場合には、前記上限値を超えてその厚みを厚くすることができる。
次に、図2に示した基礎基板40の製造工程と並行して、図3に示す配線基板3の製造工程(配線基板の製造方法)が行われる。
ここで、図15を参照して、図3に示す配線基板の製造工程を詳細に説明する。なお、図15は配線基板3を詳述するための断面拡大図である。
次に、酸化シリコン膜10b上に第1の配線パターン11aを形成する。当該第1の配線パターン11aは、積層構造であることが好ましく、本実施形態では、チタニウム、アルミ銅合金、及び窒化チタニウムからなる3層構造(Ti/Al・Cu/TiN)を採用している。また、各層膜の膜厚はそれぞれ20nm、300nm、100nm程度であることが好ましい。
次に、第1の配線パターン11a上に樹脂絶縁膜10cを形成する。当該樹脂絶縁膜10cは、アクリル樹脂によって形成されることが好ましく、その膜厚は2600nm程度であることが好ましい。
次に、第2の配線パターン11b上に樹脂絶縁膜10cを形成する。当該樹脂絶縁膜10cは、先に記載した材料及び膜厚によって形成される。
次に、第3の配線パターン11c上に樹脂絶縁膜10cを形成する。当該樹脂絶縁膜10cは、先に記載した材料及び膜厚によって形成される。
更に、3層目に形成された樹脂絶縁膜10cの一部を除去することにより、第3の配線パターン11cが露出状態となり、当該露出部分は後の工程でメッキを形成するためのAlパッドからなる電極パッド17となる。
なお、本実施形態においては、3層構造の配線パターンを用いたが、2層構造であってもよい。
次に、図3から図14を参照して、上記の配線基板3と基礎基板40とを貼り合わせて、TFT13を配線基板3に転写する方法について説明する。
ここで、転写工程としては公知の技術が採用されるが、本実施形態では特にSUFTLA(Surface Free Technology by Laser Ablation)(登録商標)を用いて行われる。
ここで、接着剤51の印刷部分は、配線基板3の接続端子である電極パッド17を避けた位置であり、TFT13を貼り合わせた際に、電極パッド17へ流れて濡れ広がらない位置とする。また、電極パッド17とTFT13の電極パッド13aとは、その後、無電解メッキによってバンプを成長させて接続するため、少なくとも5μm以上の隙間を保持することが好ましい。このため、接着剤51としては、フィラーや粒子などの所定寸法のスペーサを混入させたものを用いるのが好ましい。
配線基板3への接着剤51の塗布方法は印刷を用いるが、その他の転写方法でも良く、例えば、ディスペンスやフォトリソを用いても良い。
そして、基礎基板40と配線基板3とを貼り合わせたら、加熱加圧により接着剤51硬化させてTFT13を配線基板3に接着固定する。これにより、TFT13と配線基板3とが機械的に接続される。
次に、無電解メッキ処理法を用いて電極パッド13a、17間にバンプを形成し、これら電極パッド13a、17を電気的に接続する。
まず、電極パッド13a、17の表面の濡れ性向上、及び残さを除去するために処理液に浸漬する。本実施形態では、フッ酸が0.01%〜0.1%、及び硫酸が0.01%〜0.1%含有した水溶液中に1分〜5分間含浸する。あるいは0.1%〜10%の水酸化ナトリウム等のアルカリベースの水溶液に1分〜10分浸漬してもよい。
次に、ZnOを含有したpH11〜13のジンケート液中に1秒〜2分間浸漬し、パッド表面をZnに置換する。その後、5%〜30%の硝酸水溶液に1秒〜60秒浸漬し、Znを剥離する。そして、再度ジンケート浴中に1秒〜2分浸漬し、緻密なZn粒子をAl表面に析出させる。その後、無電解Niメッキ浴に浸漬し、Niメッキを形成する。
メッキ高さは2μm〜10μm程度析出させる。メッキ浴は次亜リン酸を還元剤とした浴であり、pH4〜5、浴温80℃〜95℃である。
そして、このような無電解メッキによって双方の電極パッド13a、17を電気的に接続することにより、図10に示すように、基板の反りや段差によってTFT13と配線基板3との接合位置が斜めになり、電極パッド13a、17同士の間隔にバラツキが生じたとしても、図11に示すように、これら電極パッド13a、17間に十分なメッキ析出をさせることで、確実に電気的に接続することができる。
また、上記のようにして電極パッド13a、17同士をバンプ52によって電気的に接続したら、その後、配線基板3とTFT13との間に、封止ペーストを充填しておけば、バンプ52によって接続した電極パッド13a、17間の接続箇所を確実に保護することができ、接続の信頼性を高めることができる。
次に、図12から図14を参照して、上記の配線基板3と有機EL基板4とを貼り合わせて、最終的に図1に示す電気光学装置1を形成する工程について説明する。
図12に示すように、有機EL基板4は、透明基板20上に、順に陽極22と、正孔注入/輸送層23と、有機EL素子24と、陰極25が形成された構造となっている。また、陰極25は、カソードセパレータ26が形成された状態で成膜されるので、陰極25は隣接する陰極と分離されている。
図13に示すように、配線基板3の有機EL接続部15上には導電性ペースト31が塗布されている。ここで、導電性ペースト31は銀ペーストを使用している。
この電気光学装置1は、有機EL基板4における配線基板3側から、順に陰極25、有機EL素子24、正孔注入/輸送層23、陽極22が配置された、陽極22側から発光光を取り出すトップエミッション型の有機EL装置となる。
このような電気光学装置及び基板接合体の製造方法のうち、電極パッド13a、17の接続工程においてバンプ52によって配線基板3に接続されたTFT13の導通確認を行ったところ、良好な導通が確認され、また、TFT13の破損、損傷などもなかった。
これにより、接続のために加熱加圧量を高めてTFT13を破損、損傷させるような不具合なく、TFT13と配線基板3との導通を確実に得ることができる。
また、電極パッド13a、17へ接着剤51が濡れ広がらないようにすることにより、電極パッド13a、17間において確実にバンプ52を成長させて電極パッド13a、17同士を電気的に接続することができる。
さらに、電極パッド13a、17間にて成長するバンプ52が短絡しないようにすれば、短絡による不具合を確実に防止することができる。
次に、パッドの接続工程の第2実施形態について説明する。
なお、上述の実施形態と同一部材には同一符号を付し、説明を簡略化する。
TFT13は、図18に示すような多角形状、あるいは図19に示すような矩形状の平面形状を有し、TFT13と配線基板3の双方の電極パッド13a、17は、TFT13の1チップあたり10パッドとし、TFT13の中央を除く周部に環状に配置した。
電極パッド13a、17の大きさは、5〜30μm×5〜30μmとし、パッド間のスペースは、10〜25μmとした。なお、最終的に形成するバンプ52が等方成長するため、あらかじめ横に成長する分だけ電極パッド13a、17を小さくするか、パッド間のスペースをあけておく。また、電極パッド13a、17の材質としては、Alを主成分として用いた。
次に、TFT13を配線基板3に貼り合わせ、加熱加圧により接着剤51を硬化させてTFT13を配線基板3に接着する。その後、エキシマレーザによりTFT13の剥離層41を破壊し、TFT13を転写する。
最後に、無電解メッキにより、配線基板3側の電極パッド17とTFT13側の電極パッド13aにメッキを行ない、バンプ52によって電極パッド13a、17を電気的に接続する。その他は、上記実施形態と同様である。
このようにして配線基板3に接続したTFT13は、良好な導通が確認され、また、TFT13の破損、損傷などもなかった。
次に、パッドの接続工程の第3実施形態について説明する。
上記の実施形態では、Alパッドからなる電極パッド13a、17へメッキを行う場合について説明したが、本実施形態では、Cu上やTiNなどの窒化膜上へメッキ金属を形成した。形成方法は、パッド上の残さを有機、無機のいずれかの溶液に浸漬して除去した後、パッド上のみにPd(パラジウム)触媒を付与して活性化する。その後、上記実施形態と同様に、無電解Niメッキ浴に浸漬し、Niメッキを形成する。
このようにして、配線基板3を接続したTFT13は、良好な導通が確認され、また、TFT13の破損、損傷などもなかった。
Claims (9)
- 配線基板上に電気素子を実装して基板接合体を製造する方法であって、
前記配線基板の電極パッドと前記電気素子の電極パッドとを所定間隔で配置して、前記配線基板および前記電気素子を機械的に接続する工程と、
前記配線基板の電極パッドおよび/または前記電気素子の電極パッドからバンプを成長させて、前記配線基板および前記電気素子を電気的に接続する工程と、
を有することを特徴とする基板接合体の製造方法。 - 前記機械的接続工程は、前記配線基板と前記電気素子との間に、所定寸法のスペーサを混入した接着剤を塗布することによって行うことを特徴とする請求項1に記載の基板接合体の製造方法。
- 前記接着剤の塗布は、前記配線基板の電極パッドと前記電気素子の電極パッドとを所定間隔で配置したときに、前記接着剤が前記各電極パッドに濡れ広がらないように行うことを特徴とする請求項2に記載の基板接合体の製造方法。
- 前記電気的接続工程では、無電解メッキ法により前記バンプを成長させることを特徴とする請求項1から3のいずれか1項に記載の基板接合体の製造方法。
- 前記配線基板の電極パッドおよび前記電気素子の電極パッドを、前記電気的接続工程の後に隣接する前記バンプが短絡しない大きさにあらかじめ形成しておくことを特徴とする請求項1から4のいずれか1項に記載の基板接合体の製造方法。
- 前記電気的接続工程の後に、前記配線基板と前記電気素子との間に封止材料を充填することを特徴とする請求項1から5のいずれか1項に記載の基板接合体の製造方法。
- 請求項1から6のいずれか1項に記載の基板接合体の製造方法を使用して製造したことを特徴とする基板接合体。
- 前記配線基板および前記電気素子の機械的接続部分を囲むように、前記各電極パッドが環状に配置されていることを特徴とする請求項7に記載の基板接合体。
- 発光素子を駆動するスイッチング素子が配線基板に実装されてなる電気光学装置であって、
前記配線基板の電極パッドと前記スイッチング素子の電極パッドとが所定間隔で配置されて、前記配線基板および前記スイッチング素子が機械的に接続され、
前記配線基板の電極パッドおよび/または前記スイッチング素子の電極パッドからバンプを成長させて、前記配線基板および前記スイッチング素子が電気的に接続されていることを特徴とする電気光学装置。
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JP3233535B2 (ja) * | 1994-08-15 | 2001-11-26 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5656858A (en) * | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
JPH09152979A (ja) * | 1995-09-28 | 1997-06-10 | Matsushita Electric Ind Co Ltd | 半導体装置 |
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JP2957955B2 (ja) | 1996-08-29 | 1999-10-06 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
WO2001018851A1 (en) * | 1999-09-03 | 2001-03-15 | Teraconnect, Inc. | Method for integration of integrated circuit devices |
JP3216130B2 (ja) | 1999-12-10 | 2001-10-09 | ソニーケミカル株式会社 | 接続構造体の製造方法 |
EP1264520A4 (en) * | 2000-03-10 | 2007-02-28 | Chippac Inc | PACKAGING STRUCTURE AND METHOD |
JP4019305B2 (ja) | 2001-07-13 | 2007-12-12 | セイコーエプソン株式会社 | 薄膜装置の製造方法 |
JP4417596B2 (ja) * | 2001-09-19 | 2010-02-17 | 富士通株式会社 | 電子部品の実装方法 |
US6858943B1 (en) * | 2003-03-25 | 2005-02-22 | Sandia Corporation | Release resistant electrical interconnections for MEMS devices |
-
2004
- 2004-03-18 JP JP2004078284A patent/JP4274013B2/ja not_active Expired - Lifetime
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2005
- 2005-03-07 US US11/074,351 patent/US7521797B2/en active Active
- 2005-03-09 CN CNB2005100541408A patent/CN100364042C/zh active Active
- 2005-03-15 TW TW094107895A patent/TWI263333B/zh active
- 2005-03-17 KR KR1020050022160A patent/KR100711377B1/ko active IP Right Grant
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KR20060043738A (ko) | 2006-05-15 |
TW200541068A (en) | 2005-12-16 |
TWI263333B (en) | 2006-10-01 |
CN1670907A (zh) | 2005-09-21 |
US20050205992A1 (en) | 2005-09-22 |
KR100711377B1 (ko) | 2007-04-30 |
CN100364042C (zh) | 2008-01-23 |
US7521797B2 (en) | 2009-04-21 |
JP4274013B2 (ja) | 2009-06-03 |
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