JP2005191149A - 混成集積回路装置の製造方法 - Google Patents
混成集積回路装置の製造方法 Download PDFInfo
- Publication number
- JP2005191149A JP2005191149A JP2003428412A JP2003428412A JP2005191149A JP 2005191149 A JP2005191149 A JP 2005191149A JP 2003428412 A JP2003428412 A JP 2003428412A JP 2003428412 A JP2003428412 A JP 2003428412A JP 2005191149 A JP2005191149 A JP 2005191149A
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- Prior art keywords
- substrate
- hybrid integrated
- integrated circuit
- circuit board
- metal substrate
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 130
- 229910052751 metal Inorganic materials 0.000 claims description 98
- 239000002184 metal Substances 0.000 claims description 98
- 238000003825 pressing Methods 0.000 claims description 16
- 238000005452 bending Methods 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 49
- 229920005989 resin Polymers 0.000 description 25
- 239000011347 resin Substances 0.000 description 25
- 238000007789 sealing Methods 0.000 description 23
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 238000005520 cutting process Methods 0.000 description 11
- 238000000926 separation method Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000004080 punching Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000010397 one-hybrid screening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
【解決手段】 本発明の混成集積回路装置の製造方法は、金属から成る金属基板19の表面に導電パターン18から成るユニット32を複数個形成する工程と、金属基板19の各ユニット32の境界に溝20を形成する工程と、各ユニット32の導電パターン19に回路素子14を電気的に接続する工程と、溝20に沿って金属基板19Bを分割することに個々の回路基板16を分離する工程と、回路基板16の側面部を押圧することにより側面を平坦化する工程とを具備する。
【選択図】図7
Description
本工程は、大判の金属基板19Aを分割することにより、中板の金属基板19Bを形成する工程である。
本工程は、中板の金属基板19Bの表面および裏面に格子状に第1の溝20Aおよび第2の溝20Bを形成する工程である。図3(A)は前工程にて分割された中板の金属基板19Bの平面図であり、図3(B)はVカットソー35を用いて金属基板19Aに溝を形成する状態を示す斜視図であり、図3(C)は刃先35Aの拡大図である。
本工程は、導電パターン18上に回路素子14を実装し、回路素子14と導電パターン18との電気的接続を行う工程である。
本工程は、金属基板19Bを溝20が形成された箇所で分割することにより個々のユニットである回路基板16を分離する工程である。ここのユニットを分離数方法としては数々の方法があるが、ここでは、折り曲げにより分離する方法と、カッターを用いて分離を行う方法を説明する。
本工程では、前行程で個別に分離した回路基板16の側面を押圧する。図10(A)は本工程を示す斜視図であり、図10(B)はその断面図である。
図11を参照して、回路基板16を封止樹脂12で封止する工程を説明する。図11は、金型50を用いて回路基板16を封止樹脂12で封止する工程を示す断面図である。
11 リード
12 封止樹脂
14 回路素子
15 金属細線
16 回路基板
17 絶縁層
Claims (10)
- 基板の表面に導電パターンから成るユニットを複数個形成する工程と、
前記各ユニットの前記導電パターンに回路素子を電気的に接続する工程と、
前記ユニットの境界で前記基板を分割することに個々の回路基板を分離する工程と、
前記回路基板の側面部を押圧することにより前記側面を平坦化する工程とを具備することを特徴とする混成集積回路装置の製造方法。 - 金属から成る基板の表面に導電パターンから成るユニットを複数個形成する工程と、
前記基板の前記各ユニットの境界に溝を形成する工程と、
前記各ユニットの前記導電パターンに回路素子を電気的に接続する工程と、
前記溝に沿って前記基板を分割することに個々の回路基板を分離する工程と、
前記回路基板の側面部を押圧することにより前記側面を平坦化する工程とを具備することを特徴とする混成集積回路装置の製造方法。 - 前記溝は、前記基板の表面に形成された第1の溝と、前記基板の裏面に形成された第2の溝から成ることを特徴とする請求項2記載の混成集積回路装置の製造方法。
- 前記溝が形成された箇所で前記基板を曲折することにより前記基板の分離を行うことを特徴とする請求項2記載の混成集積回路装置の製造方法。
- 前記基板の側面を狭持して前記基板を曲折することを特徴とする請求項4記載の混成集積回路装置の製造方法。
- 前記ユニットはマトリックス状に複数個が形成されることを特徴とする請求項1または請求項2記載の混成集積回路装置の製造方法。
- 金属から成る基板の表面に導電パターンから成るユニットを複数個形成する工程と、
前記基板の前記各ユニットの境界に溝を形成する工程と、
前記各ユニットの前記導電パターンに回路素子を電気的に接続する工程と、
前記溝に沿って前記基板を曲折することにより、個々の回路基板を分離する工程とを具備することを特徴とする混成集積回路装置の製造方法。 - 前記溝は、前記基板の表面に形成された第1の溝と、前記基板の裏面に形成された第2の溝から成ることを特徴とする請求項7記載の混成集積回路装置の製造方法。
- 前記基板の側面を狭持して前記基板を曲折することを特徴とする請求項7記載の混成集積回路装置の製造方法。
- 前記ユニットはマトリックス状に複数個が形成されることを特徴とする請求項7記載の混成集積回路装置の製造方法。
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TW93136244A TWI302425B (en) | 2003-12-24 | 2004-11-25 | Method for making a hybrid integrated circuit device |
KR20040107683A KR100574725B1 (ko) | 2003-12-24 | 2004-12-17 | 혼성 집적 회로 장치의 제조 방법 |
CNB2004101021548A CN100461353C (zh) | 2003-12-24 | 2004-12-20 | 混合集成电路装置的制造方法 |
US10/905,238 US7253027B2 (en) | 2003-12-24 | 2004-12-22 | Method of manufacturing hybrid integrated circuit device |
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CN1645579A (zh) | 2005-07-27 |
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