JP2005109526A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2005109526A JP2005109526A JP2005008264A JP2005008264A JP2005109526A JP 2005109526 A JP2005109526 A JP 2005109526A JP 2005008264 A JP2005008264 A JP 2005008264A JP 2005008264 A JP2005008264 A JP 2005008264A JP 2005109526 A JP2005109526 A JP 2005109526A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- semiconductor element
- resin
- metal body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
【解決手段】 本発明の半導体装置1は、半導体チップ2と、この半導体チップ2の両面から放熱するための一対のヒートシンク3、4とを備え、装置のほぼ全体を樹脂7でモールドしたものにおいて、半導体チップ2の厚さ寸法をt1とし、一対のヒートシンク3、4のうちの少なくとも一方のヒートシンク3の厚さ寸法をt2としたときに、t2/t1≧5が成立するように構成したものである。本発明者らは、上記構成の半導体装置1に対して大きな熱応力が作用しても、素子破壊が発生しないことを試作と実験により確認した。
【選択図】 図1
Description
Claims (10)
- 半導体素子と、この半導体素子の裏面に接合され電極と放熱を兼ねる第1の金属体と、前記半導体素子の表面側に接合され電極と放熱を兼ねる第2の金属体と、前記半導体素子の表面と前記第2の金属体との間に接合された第3の金属体とを備え、前記一対の放熱板の一面が露出するように装置のほぼ全体を樹脂でモールドした半導体装置において、
前記半導体素子と前記金属体とを接合する接合層における塑性歪み率が1%以下となるように、前記半導体素子の厚さを250μm以下とすると共に、
前記モールド樹脂により装置全体を拘束保持するように構成したことを特徴とする半導体装置。 - 半導体素子と、この半導体素子の裏面に接合され電極と放熱を兼ねる第1の金属体と、前記半導体素子の表面側に接合され電極と放熱を兼ねる第2の金属体と、前記半導体素子の表面と前記第2の金属体との間に接合された第3の金属体とを備え、前記一対の放熱板の一面が露出するように装置のほぼ全体を樹脂でモールドした半導体装置において、
前記半導体素子表面のせん断応力が35MPa以下となるように、前記半導体素子の厚さを250μm以下とすると共に、
前記モールド樹脂により装置全体を拘束保持するように構成したことを特徴とする半導体装置。 - 前記3個の金属体のうちの少なくとも1つの金属体の厚みを1.0mm以上としたことを特徴とする請求項1または2記載の半導体装置。
- 前記接合層をSn系はんだで構成したことを特徴とする請求項1ないし3のいずれかに記載の半導体装置。
- 前記半導体素子のデバイス構造を、トレンチゲートタイプとしたことを特徴とする請求項1ないし4のいずれかに記載の半導体装置。
- 前記半導体素子の厚さ寸法をt1とし、前記第1の金属体または前記第2の金属体のうちの少なくとも一方の放熱板の厚さ寸法をt2としたときに、
t2/t1≧5
が成立するように構成したことを特徴とする請求項1または2に記載の半導体装置。 - 前記金属体の熱膨張係数をα1とし、前記樹脂の熱膨張係数をα2としたときに、
0.5α1≦α2≦1.5α1
が成立するように構成したことを特徴とする請求項1または2に記載の半導体装置。 - 前記半導体素子の裏面の面粗度をRaとしたときに、
Ra≦500nm
が成立するように構成したことを特徴とする請求項1または2に記載の半導体装置。 - 前記一対の放熱板は、その一面が前記樹脂から露出するようにモールドされていることを特徴とする請求項1ないし8のいずれかに記載の半導体装置。
- 前記半導体素子と前記第1の金属体とは、接合層により直接接合されていることを特徴とする請求項1ないし9のいずれかに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005008264A JP4376798B2 (ja) | 2001-07-26 | 2005-01-14 | 半導体装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001225963 | 2001-07-26 | ||
JP2005008264A JP4376798B2 (ja) | 2001-07-26 | 2005-01-14 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002196140A Division JP2003110064A (ja) | 2001-07-26 | 2002-07-04 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007286138A Division JP2008078679A (ja) | 2001-07-26 | 2007-11-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005109526A true JP2005109526A (ja) | 2005-04-21 |
JP4376798B2 JP4376798B2 (ja) | 2009-12-02 |
Family
ID=34553993
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005008264A Expired - Lifetime JP4376798B2 (ja) | 2001-07-26 | 2005-01-14 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4376798B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7692294B2 (en) | 2006-09-14 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for fabricating the same |
JP2014013931A (ja) * | 2013-09-12 | 2014-01-23 | Denso Corp | 半導体パッケージ |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58165348A (ja) * | 1982-03-26 | 1983-09-30 | Hitachi Ltd | 半導体装置の配線板 |
JPS63142640A (ja) * | 1986-12-05 | 1988-06-15 | Sumitomo Electric Ind Ltd | 半導体装置の製造方法 |
JPH053205A (ja) * | 1991-01-25 | 1993-01-08 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
JPH07235672A (ja) * | 1994-02-21 | 1995-09-05 | Mitsubishi Electric Corp | 絶縁ゲート型半導体装置およびその製造方法 |
JPH0883859A (ja) * | 1994-09-09 | 1996-03-26 | Sony Corp | 半導体装置の製造方法 |
JPH08222668A (ja) * | 1994-12-13 | 1996-08-30 | Sumitomo Metal Ind Ltd | Icパッケージ |
JPH10116934A (ja) * | 1996-10-09 | 1998-05-06 | Fuji Electric Co Ltd | 樹脂封止半導体装置およびその製造方法 |
JP2000049281A (ja) * | 1998-07-31 | 2000-02-18 | Toshiba Corp | 半導体装置 |
JP2000058717A (ja) * | 1998-08-17 | 2000-02-25 | Hitachi Ltd | 平型半導体装置、及びこれを用いた変換器 |
JP2001156219A (ja) * | 1999-11-24 | 2001-06-08 | Denso Corp | 半導体装置 |
JP2001217362A (ja) * | 2000-01-31 | 2001-08-10 | Ngk Insulators Ltd | 積層放熱部材、および同放熱部材を用いたパワー半導体装置、並びにそれらの製造方法 |
JP2001284509A (ja) * | 2000-03-30 | 2001-10-12 | Hitachi Metals Ltd | Al−SiC複合体 |
-
2005
- 2005-01-14 JP JP2005008264A patent/JP4376798B2/ja not_active Expired - Lifetime
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58165348A (ja) * | 1982-03-26 | 1983-09-30 | Hitachi Ltd | 半導体装置の配線板 |
JPS63142640A (ja) * | 1986-12-05 | 1988-06-15 | Sumitomo Electric Ind Ltd | 半導体装置の製造方法 |
JPH053205A (ja) * | 1991-01-25 | 1993-01-08 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
JPH07235672A (ja) * | 1994-02-21 | 1995-09-05 | Mitsubishi Electric Corp | 絶縁ゲート型半導体装置およびその製造方法 |
JPH0883859A (ja) * | 1994-09-09 | 1996-03-26 | Sony Corp | 半導体装置の製造方法 |
JPH08222668A (ja) * | 1994-12-13 | 1996-08-30 | Sumitomo Metal Ind Ltd | Icパッケージ |
JPH10116934A (ja) * | 1996-10-09 | 1998-05-06 | Fuji Electric Co Ltd | 樹脂封止半導体装置およびその製造方法 |
JP2000049281A (ja) * | 1998-07-31 | 2000-02-18 | Toshiba Corp | 半導体装置 |
JP2000058717A (ja) * | 1998-08-17 | 2000-02-25 | Hitachi Ltd | 平型半導体装置、及びこれを用いた変換器 |
JP2001156219A (ja) * | 1999-11-24 | 2001-06-08 | Denso Corp | 半導体装置 |
JP2001217362A (ja) * | 2000-01-31 | 2001-08-10 | Ngk Insulators Ltd | 積層放熱部材、および同放熱部材を用いたパワー半導体装置、並びにそれらの製造方法 |
JP2001284509A (ja) * | 2000-03-30 | 2001-10-12 | Hitachi Metals Ltd | Al−SiC複合体 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7692294B2 (en) | 2006-09-14 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for fabricating the same |
JP2014013931A (ja) * | 2013-09-12 | 2014-01-23 | Denso Corp | 半導体パッケージ |
Also Published As
Publication number | Publication date |
---|---|
JP4376798B2 (ja) | 2009-12-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2003110064A (ja) | 半導体装置 | |
JP4319591B2 (ja) | 半導体パワーモジュール | |
US10510640B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
US7400002B2 (en) | MOSFET package | |
JP4260263B2 (ja) | 半導体装置 | |
CN107615464B (zh) | 电力用半导体装置的制造方法以及电力用半导体装置 | |
CN104756250B (zh) | 半导体装置 | |
JP3988735B2 (ja) | 半導体装置及びその製造方法 | |
JP4780085B2 (ja) | 半導体装置 | |
JP2021197445A (ja) | パワーモジュール、およびパワーモジュールの製造方法 | |
JP2019153699A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2008078679A (ja) | 半導体装置 | |
JP4376798B2 (ja) | 半導体装置 | |
JP2005129886A (ja) | 半導体装置およびその製造方法 | |
JP2017191826A (ja) | 半導体装置およびその製造方法 | |
JP5444299B2 (ja) | 半導体装置 | |
JP2003133329A (ja) | 半導体装置 | |
JP7072624B1 (ja) | 電力用半導体装置および電力用半導体装置の製造方法 | |
JP2006179732A (ja) | 半導体パワーモジュール | |
JP2000150742A (ja) | 伝熱シート、半導体装置及び伝熱シートの製造方法 | |
JP2018029149A (ja) | 電力用半導体装置およびその製造方法 | |
JP7179550B2 (ja) | セラミックス回路基板およびそれを用いた半導体装置 | |
JP2003068959A (ja) | 半導体装置 | |
JP5017228B2 (ja) | 半導体装置 | |
JP4357493B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050114 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070313 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20070904 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071102 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20071126 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20080222 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090909 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4376798 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120918 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120918 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130918 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |