JP2004336051A - 多孔質有機誘電体層を形成する方法 - Google Patents
多孔質有機誘電体層を形成する方法 Download PDFInfo
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
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Abstract
【解決手段】本発明は、有機絶縁層を形成し、絶縁層をパターン化し、絶縁層上にライナを堆積し、該構造をプラズマに露出してライナに隣接する領域内の絶縁層内に微細孔を形成する。ライナは、ライナに影響を与えることなく、プラズマがライナを貫通し、絶縁層に微細孔を形成できるように、十分薄く形成される。プラズマ処理の間、プラズマはライナに影響を及ぼすことなくライナを貫通する。プラズマ処理の後、付加的なライナを堆積することができる。この後、導体が堆積され、さらに導体の余分な部分は構造から除去される。本方法では、パターン化された構造体を有する有機絶縁層と、パターン化された構造体の裏側を覆うライナと、パターン化された構造体を充填する導体とを有する集積回路構造を形成する。絶縁層はライナに接触する絶縁層の表面領域にそった微細孔を含み、さらに微細孔はライナ(ライナは微細孔の内部に存在しない)に接触する表面領域に沿ってのみ存在する。
【選択図】 図1
Description
20、21 ハードマスク
22、23 エッチング・ストッパ
25 導体
26 基板
29 開口部
30 ライナ
40 プラズマ・ガス
50 シード材料
52 微細孔
60 絶縁材料
61 導体
Claims (20)
- a)パターン化された構造体を有する有機絶縁層と、
b)前記パターン化された構造体の裏側を覆うライナと、
c)前記パターン化された構造体を充填する導体と
を含む集積回路構造であって、前記絶縁層は前記ライナに接触する領域にそった微細孔を含む集積回路構造。 - 前記微細孔は、前記ライナに接触する前記絶縁層の前記領域に沿ってのみ存在する、請求項1に記載の集積回路構造。
- 前記ライナは、前記微細孔の内部に存在しない、請求項1に記載の集積回路構造。
- 前記絶縁層は、ポリ(アリル)エーテル、フルオロポリイミド、ビスベンゾシクロブタン、およびヒドリドオルガノシロキサン・ポリマーのうちから1つを含む、請求項1に記載の集積回路構造。
- 前記絶縁層は、前記微細孔に沿って水素、アルゴン、ヘリウム、キセノン、および窒素のうちの1つの濃度の増加を含む、請求項1に記載の集積回路構造。
- 前記ライナは、プラズマが前記ライナを貫通できるように差し支えのない厚みをもつ第1の層および前記第1の層の上に第2の層を含む、請求項1に記載の集積回路構造。
- 前記第1の層は、10乃至500オングストロームの厚みを有し、かつTa、TaN、Ti、TiN、およびWを含むグループから選択される1つ以上の材料を含む、請求項6に記載の集積回路構造。
- 前記第2の層は、10乃至500オングストロームの厚みを有し、かつTa、TaN、Ti、TiN、WおよびCuを含むグループから選択される1つ以上の材料を含む、請求項6に記載の集積回路構造。
- a)パターン化された構造体を有する有機絶縁層と、
b)前記パターン化された構造体の裏側を覆うライナであって、プラズマが前記ライナを貫通できるように差し支えのない厚みを有する第1の層を含むライナと、
c)前記パターン化された構造体を充填する導体と、
を含む集積回路構造であって、前記絶縁層は前記ライナに接触する領域にそった微細孔を含む集積回路構造。 - 前記微細孔は、前記ライナに接触する前記絶縁層の前記領域に沿ってのみ存在する、請求項9に記載の集積回路構造。
- 前記ライナは、前記微細孔の内部に存在しない、請求項9に記載の集積回路構造。
- 前記絶縁層は、ポリ(アリル)エーテル、フルオロポリイミド、ビスベンゾシクロブタン、およびヒドリドオルガノシロキサン・ポリマーのうちから1つを含む、請求項9に記載の集積回路構造。
- 前記絶縁層は、前記微細孔に沿って水素、アルゴン、ヘリウム、キセノン、および窒素のうちの1つの濃度の増加を含む、請求項9に記載の集積回路構造。
- 前記ライナは、前記第1の層の上に第2の層をさらに含む、請求項9に記載の集積回路構造。
- 前記第1の層は、10乃至500オングストロームの厚みを有し、かつTa、TaN、Ti、TiN、およびWを含むグループから選択される1つ以上の材料を含む、請求項14に記載の集積回路構造
- 前記第2の層は、10乃至500オングストロームの厚みを有し、かつTa、TaN、Ti、TiN、WおよびCuを含むグループから選択される1つ以上の材料を含む、請求項14に記載の集積回路構造
- 集積回路構造内に配線層を形成する方法であって、
a)有機絶縁層を形成する工程と、
b)前記絶縁層をパタニングする工程と、
c)前記絶縁層上にライナを堆積する工程と、
d)前記構造をプラズマに露出して前記ライナの真下に微細孔を形成する工程と、
を含む方法。 - 前記ライナの前記堆積は、前記プラズマが前記ライナを貫通し、前記絶縁層内に微細孔を形成できるように差し支えのない厚みまで前記ライナを形成する、請求項17に記載の方法。
- 前記ライナの前記堆積は、前記ライナが10乃至500オングストロームの厚みを有するように形成する、請求項17に記載の方法。
- 前記露出工程の間、前記プラズマは前記ライナに影響を及ぼすことなく、前記ライナを貫通する、請求項17に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/249,799 US6921978B2 (en) | 2003-05-08 | 2003-05-08 | Method to generate porous organic dielectric |
Publications (2)
Publication Number | Publication Date |
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JP2004336051A true JP2004336051A (ja) | 2004-11-25 |
JP4086811B2 JP4086811B2 (ja) | 2008-05-14 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004136335A Expired - Fee Related JP4086811B2 (ja) | 2003-05-08 | 2004-04-30 | 多孔質有機誘電体層を形成する方法 |
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Country | Link |
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US (2) | US6921978B2 (ja) |
JP (1) | JP4086811B2 (ja) |
CN (1) | CN100382301C (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012023245A (ja) * | 2010-07-15 | 2012-02-02 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
US9975966B2 (en) | 2014-09-26 | 2018-05-22 | Chugai Seiyaku Kabushiki Kaisha | Cytotoxicity-inducing theraputic agent |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6919636B1 (en) | 2003-07-31 | 2005-07-19 | Advanced Micro Devices, Inc. | Interconnects with a dielectric sealant layer |
JP2007053133A (ja) * | 2005-08-15 | 2007-03-01 | Toshiba Corp | 半導体装置及びその製造方法 |
US20070278682A1 (en) * | 2006-05-31 | 2007-12-06 | Chung-Chi Ko | Self-assembled mono-layer liner for cu/porous low-k interconnections |
JP2009147096A (ja) * | 2007-12-14 | 2009-07-02 | Panasonic Corp | 半導体装置及びその製造方法 |
US7875519B2 (en) * | 2008-05-21 | 2011-01-25 | Intel Corporation | Metal gate structure and method of manufacturing same |
US8679970B2 (en) * | 2008-05-21 | 2014-03-25 | International Business Machines Corporation | Structure and process for conductive contact integration |
US8980740B2 (en) | 2013-03-06 | 2015-03-17 | Globalfoundries Inc. | Barrier layer conformality in copper interconnects |
US9613906B2 (en) * | 2014-06-23 | 2017-04-04 | GlobalFoundries, Inc. | Integrated circuits including modified liners and methods for fabricating the same |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5472913A (en) * | 1994-08-05 | 1995-12-05 | Texas Instruments Incorporated | Method of fabricating porous dielectric material with a passivation layer for electronics applications |
US6214423B1 (en) * | 1998-04-16 | 2001-04-10 | Texas Instruments Incorporated | Method of forming a polymer on a surface |
US6171945B1 (en) * | 1998-10-22 | 2001-01-09 | Applied Materials, Inc. | CVD nanoporous silica low dielectric constant films |
US6159842A (en) * | 1999-01-11 | 2000-12-12 | Taiwan Semiconductor Manufacturing Company | Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections |
US6399666B1 (en) * | 1999-01-27 | 2002-06-04 | International Business Machines Corporation | Insulative matrix material |
JP3888794B2 (ja) * | 1999-01-27 | 2007-03-07 | 松下電器産業株式会社 | 多孔質膜の形成方法、配線構造体及びその形成方法 |
JP3084367B1 (ja) * | 1999-03-17 | 2000-09-04 | キヤノン販売株式会社 | 層間絶縁膜の形成方法及び半導体装置 |
US6277765B1 (en) * | 1999-08-17 | 2001-08-21 | Intel Corporation | Low-K Dielectric layer and method of making same |
US6420441B1 (en) * | 1999-10-01 | 2002-07-16 | Shipley Company, L.L.C. | Porous materials |
US6342454B1 (en) * | 1999-11-16 | 2002-01-29 | International Business Machines Corporation | Electronic devices with dielectric compositions and method for their manufacture |
GB0001179D0 (en) * | 2000-01-19 | 2000-03-08 | Trikon Holdings Ltd | Methods & apparatus for forming a film on a substrate |
US6326692B1 (en) * | 2000-02-23 | 2001-12-04 | Advanced Micro Devices, Inc. | Insulating and capping structure with preservation of the low dielectric constant of the insulating layer |
US6284657B1 (en) * | 2000-02-25 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Non-metallic barrier formation for copper damascene type interconnects |
JP2001308175A (ja) * | 2000-04-21 | 2001-11-02 | Nec Corp | 半導体装置及びその製造方法 |
US6323121B1 (en) * | 2000-05-12 | 2001-11-27 | Taiwan Semiconductor Manufacturing Company | Fully dry post-via-etch cleaning method for a damascene process |
AU2001288954A1 (en) * | 2000-09-13 | 2002-03-26 | Shipley Company, L.L.C. | Electronic device manufacture |
EP1195801B1 (en) * | 2000-09-29 | 2014-01-29 | Imec | Process for plasma treating an isolation layer with low permittivity |
US6451712B1 (en) * | 2000-12-18 | 2002-09-17 | International Business Machines Corporation | Method for forming a porous dielectric material layer in a semiconductor device and device formed |
US6355563B1 (en) * | 2001-03-05 | 2002-03-12 | Chartered Semiconductor Manufacturing Ltd. | Versatile copper-wiring layout design with low-k dielectric integration |
US6964919B2 (en) * | 2002-08-12 | 2005-11-15 | Intel Corporation | Low-k dielectric film with good mechanical strength |
US7404990B2 (en) * | 2002-11-14 | 2008-07-29 | Air Products And Chemicals, Inc. | Non-thermal process for forming porous low dielectric constant films |
-
2003
- 2003-05-08 US US10/249,799 patent/US6921978B2/en not_active Expired - Fee Related
-
2004
- 2004-04-29 CN CNB2004100366620A patent/CN100382301C/zh not_active Expired - Fee Related
- 2004-04-30 JP JP2004136335A patent/JP4086811B2/ja not_active Expired - Fee Related
-
2005
- 2005-05-10 US US11/125,549 patent/US7101784B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012023245A (ja) * | 2010-07-15 | 2012-02-02 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
US9337093B2 (en) | 2010-07-15 | 2016-05-10 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
US9975966B2 (en) | 2014-09-26 | 2018-05-22 | Chugai Seiyaku Kabushiki Kaisha | Cytotoxicity-inducing theraputic agent |
US11001643B2 (en) | 2014-09-26 | 2021-05-11 | Chugai Seiyaku Kabushiki Kaisha | Cytotoxicity-inducing therapeutic agent |
Also Published As
Publication number | Publication date |
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JP4086811B2 (ja) | 2008-05-14 |
US7101784B2 (en) | 2006-09-05 |
US6921978B2 (en) | 2005-07-26 |
US20040224494A1 (en) | 2004-11-11 |
CN100382301C (zh) | 2008-04-16 |
CN1551346A (zh) | 2004-12-01 |
US20050200024A1 (en) | 2005-09-15 |
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