JP2004221473A5 - - Google Patents

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Publication number
JP2004221473A5
JP2004221473A5 JP2003009733A JP2003009733A JP2004221473A5 JP 2004221473 A5 JP2004221473 A5 JP 2004221473A5 JP 2003009733 A JP2003009733 A JP 2003009733A JP 2003009733 A JP2003009733 A JP 2003009733A JP 2004221473 A5 JP2004221473 A5 JP 2004221473A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003009733A
Other versions
JP2004221473A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2003009733A priority Critical patent/JP2004221473A/ja
Priority claimed from JP2003009733A external-priority patent/JP2004221473A/ja
Priority to US10/606,240 priority patent/US6903961B2/en
Priority to TW092120069A priority patent/TWI222643B/zh
Priority to DE10334424A priority patent/DE10334424A1/de
Priority to KR10-2003-0061964A priority patent/KR100538589B1/ko
Priority to CNB031589022A priority patent/CN100367408C/zh
Publication of JP2004221473A publication Critical patent/JP2004221473A/ja
Priority to US11/131,384 priority patent/US7072204B2/en
Publication of JP2004221473A5 publication Critical patent/JP2004221473A5/ja
Pending legal-status Critical Current

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JP2003009733A 2003-01-17 2003-01-17 半導体記憶装置 Pending JP2004221473A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2003009733A JP2004221473A (ja) 2003-01-17 2003-01-17 半導体記憶装置
US10/606,240 US6903961B2 (en) 2003-01-17 2003-06-26 Semiconductor memory device having twin-cell units
TW092120069A TWI222643B (en) 2003-01-17 2003-07-23 Semiconductor memory device
DE10334424A DE10334424A1 (de) 2003-01-17 2003-07-28 Halbleiterspeichervorrichtung mit Doppelzelleneinheiten
KR10-2003-0061964A KR100538589B1 (ko) 2003-01-17 2003-09-05 트윈셀을 구비한 반도체 기억 장치
CNB031589022A CN100367408C (zh) 2003-01-17 2003-09-08 设有双单元的半导体存储装置
US11/131,384 US7072204B2 (en) 2003-01-17 2005-05-18 Semiconductor memory device having dummy word line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003009733A JP2004221473A (ja) 2003-01-17 2003-01-17 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2004221473A JP2004221473A (ja) 2004-08-05
JP2004221473A5 true JP2004221473A5 (ja) 2006-03-02

Family

ID=32677523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003009733A Pending JP2004221473A (ja) 2003-01-17 2003-01-17 半導体記憶装置

Country Status (6)

Country Link
US (2) US6903961B2 (ja)
JP (1) JP2004221473A (ja)
KR (1) KR100538589B1 (ja)
CN (1) CN100367408C (ja)
DE (1) DE10334424A1 (ja)
TW (1) TWI222643B (ja)

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US20040119105A1 (en) * 2002-12-18 2004-06-24 Wilson Dennis Robert Ferroelectric memory
US7251159B2 (en) * 2004-01-09 2007-07-31 Broadcom Corporation Data encoding approach for implementing robust non-volatile memories
US7547936B2 (en) * 2004-10-08 2009-06-16 Samsung Electronics Co., Ltd. Semiconductor memory devices including offset active regions
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US7254089B2 (en) * 2004-12-29 2007-08-07 Infineon Technologies Ag Memory with selectable single cell or twin cell configuration
DE102005003461A1 (de) * 2005-01-25 2006-08-03 Infineon Technologies Ag Integrierter Halbleiterspeicher und Verfahren zum Betreiben eines Halbleiterspeichers
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US20070038804A1 (en) * 2005-08-12 2007-02-15 Klaus Nierle Testmode and test method for increased stress duty cycles during burn in
US7164595B1 (en) * 2005-08-25 2007-01-16 Micron Technology, Inc. Device and method for using dynamic cell plate sensing in a DRAM memory cell
US7375999B2 (en) * 2005-09-29 2008-05-20 Infineon Technologies Ag Low equalized sense-amp for twin cell DRAMs
KR100810060B1 (ko) * 2006-04-14 2008-03-05 주식회사 하이닉스반도체 반도체 메모리 소자 및 그의 구동방법
CN101131856B (zh) * 2006-08-23 2011-01-26 旺宏电子股份有限公司 用于存储器单元的数据储存方法
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US7916567B2 (en) * 2008-03-07 2011-03-29 ProMOS Technologies Pte. Ltd Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM
KR101442175B1 (ko) * 2008-05-23 2014-09-18 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 메모리 셀 어레이의 배치방법
JP5665266B2 (ja) * 2008-08-07 2015-02-04 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
KR20100071211A (ko) * 2008-12-19 2010-06-29 삼성전자주식회사 셀 어레이로 인가되는 리키지 커런트를 막는 더미 셀 비트 라인 구조를 갖는 반도체 소자 및 그 형성 방법
JP2010192718A (ja) * 2009-02-19 2010-09-02 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
KR101113333B1 (ko) * 2011-02-15 2012-03-13 주식회사 하이닉스반도체 반도체 소자의 형성방법
US8519462B2 (en) * 2011-06-27 2013-08-27 Intel Corporation 6F2 DRAM cell
JP5922994B2 (ja) * 2012-06-13 2016-05-24 ルネサスエレクトロニクス株式会社 Ｄｒａｍ装置
JP2015084270A (ja) * 2014-12-09 2015-04-30 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
DE102018117461A1 (de) * 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Schreibassistent für eine speichervorrichtung und verfahren zu dessen herstellung
US10395752B2 (en) 2017-10-11 2019-08-27 Globalfoundries Inc. Margin test for multiple-time programmable memory (MTPM) with split wordlines
JP2020047736A (ja) * 2018-09-18 2020-03-26 キオクシア株式会社 半導体装置

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