JP2004031439A - 半導体集積回路装置およびその製造方法 - Google Patents

半導体集積回路装置およびその製造方法 Download PDF

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Publication number
JP2004031439A
JP2004031439A JP2002181974A JP2002181974A JP2004031439A JP 2004031439 A JP2004031439 A JP 2004031439A JP 2002181974 A JP2002181974 A JP 2002181974A JP 2002181974 A JP2002181974 A JP 2002181974A JP 2004031439 A JP2004031439 A JP 2004031439A
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Japan
Prior art keywords
wiring
insulating film
plug
buried
forming
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Pending
Application number
JP2002181974A
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English (en)
Japanese (ja)
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JP2004031439A5 (enExample
Inventor
Takako Fujii
藤井　貴子
Hidekazu Murakami
村上　英一
Kazumasa Yanagisawa
柳沢　一正
Miki Takeuchi
竹内　幹
Hideo Aoki
青木　英雄
Hide Yamaguchi
山口　日出
Takafumi Oshima
大島　隆文
Kazuyuki Tsukuni
津国　和之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002181974A priority Critical patent/JP2004031439A/ja
Priority to US10/465,541 priority patent/US7023091B2/en
Publication of JP2004031439A publication Critical patent/JP2004031439A/ja
Publication of JP2004031439A5 publication Critical patent/JP2004031439A5/ja
Priority to US11/239,371 priority patent/US7411301B2/en
Priority to US12/188,591 priority patent/US7786585B2/en
Priority to US12/764,411 priority patent/US7977238B2/en
Priority to US13/098,648 priority patent/US8093723B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2002181974A 2002-06-21 2002-06-21 半導体集積回路装置およびその製造方法 Pending JP2004031439A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2002181974A JP2004031439A (ja) 2002-06-21 2002-06-21 半導体集積回路装置およびその製造方法
US10/465,541 US7023091B2 (en) 2002-06-21 2003-06-20 Semiconductor integrated circuit device
US11/239,371 US7411301B2 (en) 2002-06-21 2005-09-30 Semiconductor integrated circuit device
US12/188,591 US7786585B2 (en) 2002-06-21 2008-08-08 Semiconductor integrated circuit device
US12/764,411 US7977238B2 (en) 2002-06-21 2010-04-21 Method of manufacturing a semiconductor integrated circuit device
US13/098,648 US8093723B2 (en) 2002-06-21 2011-05-02 Method of manufacturing a semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002181974A JP2004031439A (ja) 2002-06-21 2002-06-21 半導体集積回路装置およびその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007292929A Division JP2008053758A (ja) 2007-11-12 2007-11-12 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2004031439A true JP2004031439A (ja) 2004-01-29
JP2004031439A5 JP2004031439A5 (enExample) 2005-09-22

Family

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JP2002181974A Pending JP2004031439A (ja) 2002-06-21 2002-06-21 半導体集積回路装置およびその製造方法

Country Status (2)

Country Link
US (5) US7023091B2 (enExample)
JP (1) JP2004031439A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006054433A (ja) * 2004-07-14 2006-02-23 Internatl Business Mach Corp <Ibm> デュアル・ダマシン配線及びその形成方法
JP2006190869A (ja) * 2005-01-07 2006-07-20 Nec Electronics Corp 半導体装置の設計方法および信頼性評価方法
EP2284740A1 (en) 2009-08-11 2011-02-16 Fujitsu Semiconductor Limited Design support program, design support system, and design support method
US8309458B2 (en) 2010-05-03 2012-11-13 Samsung Electronics Co., Ltd. Semiconductor device comprising variable-sized contact, method of forming same, and apparatus comprising same
JP2020004756A (ja) * 2018-06-25 2020-01-09 ルネサスエレクトロニクス株式会社 半導体装置

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3790469B2 (ja) * 2001-12-21 2006-06-28 富士通株式会社 半導体装置
JP2004031439A (ja) * 2002-06-21 2004-01-29 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US7888672B2 (en) * 2002-11-23 2011-02-15 Infineon Technologies Ag Device for detecting stress migration properties
US9318378B2 (en) * 2004-08-21 2016-04-19 Globalfoundries Singapore Pte. Ltd. Slot designs in wide metal lines
JP2007234857A (ja) * 2006-03-01 2007-09-13 Matsushita Electric Ind Co Ltd 半導体集積回路および半導体集積回路の設計方法
JP4731456B2 (ja) 2006-12-19 2011-07-27 富士通セミコンダクター株式会社 半導体装置
JP2009295873A (ja) * 2008-06-06 2009-12-17 Panasonic Corp 半導体装置
JP4862017B2 (ja) * 2008-07-10 2012-01-25 ルネサスエレクトロニクス株式会社 中継基板、その製造方法、プローブカード
US8653648B2 (en) * 2008-10-03 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Zigzag pattern for TSV copper adhesion
KR101085721B1 (ko) * 2009-02-10 2011-11-21 주식회사 하이닉스반도체 반도체 소자 및 그 제조방법
JP5502339B2 (ja) * 2009-02-17 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP5603768B2 (ja) * 2010-12-28 2014-10-08 株式会社東芝 半導体集積回路の配線方法、半導体回路配線装置および半導体集積回路
WO2012123829A1 (en) * 2011-03-16 2012-09-20 Koninklijke Philips Electronics N.V. Method and system for intelligent linking of medical data.
JP5554303B2 (ja) 2011-09-08 2014-07-23 株式会社東芝 半導体集積回路および半導体集積回路の設計方法
JP5802534B2 (ja) * 2011-12-06 2015-10-28 株式会社東芝 半導体装置
CN105097954B (zh) * 2014-05-23 2018-11-16 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和电子装置
JP6597215B2 (ja) * 2015-11-16 2019-10-30 富士電機株式会社 半導体装置の製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
JPS6490544A (en) 1987-10-01 1989-04-07 Matsushita Electronics Corp Semiconductor integrated circuit
US5019877A (en) * 1989-08-31 1991-05-28 Mitsubishi Denki Kabushiki Kaisha Field effect transistor
JPH03145743A (ja) 1989-10-31 1991-06-20 Hitachi Ltd 半導体集積回路装置
US5625232A (en) * 1994-07-15 1997-04-29 Texas Instruments Incorporated Reliability of metal leads in high speed LSI semiconductors using dummy vias
JPH08316330A (ja) 1995-05-12 1996-11-29 Hitachi Ltd 半導体集積回路のレイアウト方法
JPH1174355A (ja) 1997-06-27 1999-03-16 Toshiba Corp 半導体装置の製造方法
US6731007B1 (en) * 1997-08-29 2004-05-04 Hitachi, Ltd. Semiconductor integrated circuit device with vertically stacked conductor interconnections
JP3415081B2 (ja) 1999-10-19 2003-06-09 沖電気工業株式会社 半導体装置及び半導体装置の製造方法
JP4258914B2 (ja) 1999-10-19 2009-04-30 富士通株式会社 半導体装置
JP2001337440A (ja) 2000-03-24 2001-12-07 Toshiba Corp 半導体集積回路のパターン設計方法、フォトマスク、および半導体装置
JP3819670B2 (ja) 2000-04-14 2006-09-13 富士通株式会社 ダマシン配線を有する半導体装置
JP2002124565A (ja) 2000-10-12 2002-04-26 Fujitsu Ltd 多層配線構造を有する半導体装置
JP2002164428A (ja) * 2000-11-29 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
JP2003303885A (ja) * 2002-04-08 2003-10-24 Mitsubishi Electric Corp 集積回路及びその設計方法
US20030218259A1 (en) * 2002-05-21 2003-11-27 Chesire Daniel Patrick Bond pad support structure for a semiconductor device
JP2004031439A (ja) * 2002-06-21 2004-01-29 Renesas Technology Corp 半導体集積回路装置およびその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006054433A (ja) * 2004-07-14 2006-02-23 Internatl Business Mach Corp <Ibm> デュアル・ダマシン配線及びその形成方法
JP2006190869A (ja) * 2005-01-07 2006-07-20 Nec Electronics Corp 半導体装置の設計方法および信頼性評価方法
EP2284740A1 (en) 2009-08-11 2011-02-16 Fujitsu Semiconductor Limited Design support program, design support system, and design support method
US8468481B2 (en) 2009-08-11 2013-06-18 Fujitsu Semiconductor Limited Support program, design support system, and design support method
US8309458B2 (en) 2010-05-03 2012-11-13 Samsung Electronics Co., Ltd. Semiconductor device comprising variable-sized contact, method of forming same, and apparatus comprising same
JP2020004756A (ja) * 2018-06-25 2020-01-09 ルネサスエレクトロニクス株式会社 半導体装置
JP7085417B2 (ja) 2018-06-25 2022-06-16 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US8093723B2 (en) 2012-01-10
US7023091B2 (en) 2006-04-04
US20110204486A1 (en) 2011-08-25
US20080303158A1 (en) 2008-12-11
US20060027928A1 (en) 2006-02-09
US7977238B2 (en) 2011-07-12
US7786585B2 (en) 2010-08-31
US20040065961A1 (en) 2004-04-08
US7411301B2 (en) 2008-08-12
US20100203724A1 (en) 2010-08-12

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