JP2003518738A - シリコンの金属マスクエッチング方法 - Google Patents

シリコンの金属マスクエッチング方法

Info

Publication number
JP2003518738A
JP2003518738A JP2001547641A JP2001547641A JP2003518738A JP 2003518738 A JP2003518738 A JP 2003518738A JP 2001547641 A JP2001547641 A JP 2001547641A JP 2001547641 A JP2001547641 A JP 2001547641A JP 2003518738 A JP2003518738 A JP 2003518738A
Authority
JP
Japan
Prior art keywords
plasma
etching
masking material
aluminum
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001547641A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003518738A5 (enExample
Inventor
アジェイ クマー
アニスル カーン
ウェイ リウ
ジョン チャオ
ジェフ チン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of JP2003518738A publication Critical patent/JP2003518738A/ja
Publication of JP2003518738A5 publication Critical patent/JP2003518738A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
JP2001547641A 1999-12-20 2000-12-20 シリコンの金属マスクエッチング方法 Pending JP2003518738A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/467,560 US6491835B1 (en) 1999-12-20 1999-12-20 Metal mask etching of silicon
US09/467,560 1999-12-20
PCT/US2000/034684 WO2001047005A1 (en) 1999-12-20 2000-12-20 Metal mask etching of silicon

Publications (2)

Publication Number Publication Date
JP2003518738A true JP2003518738A (ja) 2003-06-10
JP2003518738A5 JP2003518738A5 (enExample) 2008-02-14

Family

ID=23856200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001547641A Pending JP2003518738A (ja) 1999-12-20 2000-12-20 シリコンの金属マスクエッチング方法

Country Status (5)

Country Link
US (1) US6491835B1 (enExample)
EP (1) EP1240665A1 (enExample)
JP (1) JP2003518738A (enExample)
KR (1) KR100808049B1 (enExample)
WO (1) WO2001047005A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006295031A (ja) * 2005-04-14 2006-10-26 Fuji Electric Holdings Co Ltd 半導体装置の製造方法
JP4791956B2 (ja) * 2003-03-03 2011-10-12 ラム リサーチ コーポレーション プラズマエッチングチャンバ内でポリシリコンゲート構造をエッチングするための方法、及び基板の異なるドープ済み材料の間のエッチング速度のマイクロローディングを減少させる方法
JP2014116567A (ja) * 2012-12-12 2014-06-26 Tokyo Electron Ltd プラズマエッチング方法及びプラズマエッチング装置
JP2020522137A (ja) * 2017-05-26 2020-07-27 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ ハイブリッドレーザスクライビングおよびプラズマエッチングウエハ個片化プロセスのための光吸収マスク

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10204222B4 (de) * 2002-01-31 2005-12-01 Infineon Technologies Ag Verfahren zur Seitenwandpassivierung beim Plasmaätzen
DE10237249B4 (de) 2002-08-14 2014-12-18 Excelitas Technologies Singapore Pte Ltd Verfahren zum selektiven Abtragen von Material aus der Oberfläche eines Substrats
KR101155841B1 (ko) * 2003-03-03 2012-06-20 램 리써치 코포레이션 이중 도핑된 게이트 애플리케이션에서 프로파일 제어 및ｎ／ｐ 로딩을 개선하는 방법
US7141505B2 (en) * 2003-06-27 2006-11-28 Lam Research Corporation Method for bilayer resist plasma etch
DE10331526A1 (de) * 2003-07-11 2005-02-03 Infineon Technologies Ag Verfahren zum anisotropen Ätzen einer Ausnehmung in ein Siliziumsubstrat und Verwendung einer Plasmaätzanlage
US20050227382A1 (en) * 2004-04-02 2005-10-13 Hui Angela T In-situ surface treatment for memory cell formation
US20050269286A1 (en) * 2004-06-08 2005-12-08 Manish Sharma Method of fabricating a nano-wire
US7344954B2 (en) * 2006-01-03 2008-03-18 United Microelectonics Corp. Method of manufacturing a capacitor deep trench and of etching a deep trench opening
KR101059709B1 (ko) * 2006-07-14 2011-08-29 가부시키가이샤 알박 반도체 장치의 제조 방법
JP2008098281A (ja) * 2006-10-10 2008-04-24 Toshiba Corp 半導体装置の製造方法
US7704849B2 (en) * 2007-12-03 2010-04-27 Micron Technology, Inc. Methods of forming trench isolation in silicon of a semiconductor substrate by plasma
KR101588909B1 (ko) * 2007-12-21 2016-02-12 램 리써치 코포레이션 실리콘 구조의 제조 및 프로파일 제어를 이용한 딥 실리콘 에칭
US9018098B2 (en) * 2008-10-23 2015-04-28 Lam Research Corporation Silicon etch with passivation using chemical vapor deposition
US8173547B2 (en) * 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
CN102590924B (zh) * 2011-01-07 2014-08-20 志圣工业股份有限公司 导光板制造方法、导光板及罩板
US8993437B2 (en) 2011-10-27 2015-03-31 Infineon Technologies Ag Method for etching substrate
JP6396819B2 (ja) * 2015-02-03 2018-09-26 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
CN109698274B (zh) 2017-10-23 2021-05-25 联华电子股份有限公司 电容的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249783A (ja) * 1994-03-10 1995-09-26 Fuji Electric Co Ltd ダイヤフラムの製造方法
JPH09289213A (ja) * 1996-04-22 1997-11-04 Sony Corp 高融点金属配線形成方法
JPH1192971A (ja) * 1997-09-22 1999-04-06 Natl Res Inst For Metals 反応性イオンエッチング用のマスク
WO1999030359A1 (en) * 1997-12-05 1999-06-17 Applied Materials, Inc. New etch process for forming high aspect ratio trenches in silicon

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US3795557A (en) * 1972-05-12 1974-03-05 Lfe Corp Process and material for manufacturing semiconductor devices
DE3026911A1 (de) * 1980-07-16 1982-02-04 Philips Patentverwaltung Gmbh, 2000 Hamburg Verfahren zum hochfrequenz-kathodenzerstaeubungs-aetzen von loechern in einem substrat
EP0222739A3 (de) 1985-11-13 1989-10-04 IMS Ionen Mikrofabrikations Systeme Gesellschaft m.b.H. Verfahren zur Herstellung einer Transmissionsmaske
RU2009576C1 (ru) 1991-05-12 1994-03-15 Концерн "Зейф" Способ изготовления структур кремний на диэлектрике
US5368685A (en) 1992-03-24 1994-11-29 Hitachi, Ltd. Dry etching apparatus and method
JP3334911B2 (ja) 1992-07-31 2002-10-15 キヤノン株式会社 パターン形成方法
JPH06151382A (ja) * 1992-11-11 1994-05-31 Toshiba Corp ドライエッチング方法
US5536364A (en) 1993-06-04 1996-07-16 Nippon Soken, Inc. Process of plasma etching silicon
JP3309620B2 (ja) 1995-01-27 2002-07-29 富士電機株式会社 ドライエッチングによる部品の製造方法
US5605603A (en) 1995-03-29 1997-02-25 International Business Machines Corporation Deep trench process
US6287975B1 (en) 1998-01-20 2001-09-11 Tegal Corporation Method for using a hard mask for critical dimension growth containment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249783A (ja) * 1994-03-10 1995-09-26 Fuji Electric Co Ltd ダイヤフラムの製造方法
JPH09289213A (ja) * 1996-04-22 1997-11-04 Sony Corp 高融点金属配線形成方法
JPH1192971A (ja) * 1997-09-22 1999-04-06 Natl Res Inst For Metals 反応性イオンエッチング用のマスク
WO1999030359A1 (en) * 1997-12-05 1999-06-17 Applied Materials, Inc. New etch process for forming high aspect ratio trenches in silicon

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4791956B2 (ja) * 2003-03-03 2011-10-12 ラム リサーチ コーポレーション プラズマエッチングチャンバ内でポリシリコンゲート構造をエッチングするための方法、及び基板の異なるドープ済み材料の間のエッチング速度のマイクロローディングを減少させる方法
JP2011211225A (ja) * 2003-03-03 2011-10-20 Lam Research Corp デュアルドープゲートの用途におけるプロフィル制御とｎ／ｐローディングを改善する方法
JP2006295031A (ja) * 2005-04-14 2006-10-26 Fuji Electric Holdings Co Ltd 半導体装置の製造方法
JP2014116567A (ja) * 2012-12-12 2014-06-26 Tokyo Electron Ltd プラズマエッチング方法及びプラズマエッチング装置
JP2020522137A (ja) * 2017-05-26 2020-07-27 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ ハイブリッドレーザスクライビングおよびプラズマエッチングウエハ個片化プロセスのための光吸収マスク
JP7181899B2 (ja) 2017-05-26 2022-12-01 アプライド マテリアルズ インコーポレイテッド ハイブリッドレーザスクライビングおよびプラズマエッチングウエハ個片化プロセスのための光吸収マスク
JP7181899B6 (ja) 2017-05-26 2022-12-16 アプライド マテリアルズ インコーポレイテッド ハイブリッドレーザスクライビングおよびプラズマエッチングウエハ個片化プロセスのための光吸収マスク

Also Published As

Publication number Publication date
EP1240665A1 (en) 2002-09-18
US6491835B1 (en) 2002-12-10
WO2001047005A1 (en) 2001-06-28
KR20020061004A (ko) 2002-07-19
KR100808049B1 (ko) 2008-02-28

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