JP2003347373A - ウエハ上の回路を試験するシステム及び方法 - Google Patents

ウエハ上の回路を試験するシステム及び方法

Info

Publication number
JP2003347373A
JP2003347373A JP2003133508A JP2003133508A JP2003347373A JP 2003347373 A JP2003347373 A JP 2003347373A JP 2003133508 A JP2003133508 A JP 2003133508A JP 2003133508 A JP2003133508 A JP 2003133508A JP 2003347373 A JP2003347373 A JP 2003347373A
Authority
JP
Japan
Prior art keywords
dies
die
test
wafer
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003133508A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003347373A5 (enExample
Inventor
Erik H Volkerink
エリック・エイチ・ボルケリンク
Ajay Khoche
アジェイ・コーチェ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2003347373A publication Critical patent/JP2003347373A/ja
Publication of JP2003347373A5 publication Critical patent/JP2003347373A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2003133508A 2002-05-24 2003-05-12 ウエハ上の回路を試験するシステム及び方法 Pending JP2003347373A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/155,651 US7412639B2 (en) 2002-05-24 2002-05-24 System and method for testing circuitry on a wafer
US155651 2002-05-24

Publications (2)

Publication Number Publication Date
JP2003347373A true JP2003347373A (ja) 2003-12-05
JP2003347373A5 JP2003347373A5 (enExample) 2006-06-15

Family

ID=22556237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003133508A Pending JP2003347373A (ja) 2002-05-24 2003-05-12 ウエハ上の回路を試験するシステム及び方法

Country Status (3)

Country Link
US (1) US7412639B2 (enExample)
JP (1) JP2003347373A (enExample)
GB (1) GB2391706B (enExample)

Cited By (1)

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JP5269896B2 (ja) * 2008-06-02 2013-08-21 株式会社アドバンテスト 試験用ウエハユニット、および、試験システム

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JP3446124B2 (ja) * 2001-12-04 2003-09-16 科学技術振興事業団 高速入出力装置を備えた半導体集積回路装置の試験方法及び試験装置
US6777971B2 (en) * 2002-03-20 2004-08-17 Lsi Logic Corporation High speed wafer sort and final test
US7131046B2 (en) * 2002-12-03 2006-10-31 Verigy Ipco System and method for testing circuitry using an externally generated signature
US7512851B2 (en) * 2003-08-01 2009-03-31 Syntest Technologies, Inc. Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
US7279919B2 (en) * 2005-01-14 2007-10-09 Verigy (Singapore) Pte. Ltd. Systems and methods of allocating device testing resources to sites of a probe card
JP2008102045A (ja) * 2006-10-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体集積回路および半導体集積回路の検査方法
US7882405B2 (en) * 2007-02-16 2011-02-01 Atmel Corporation Embedded architecture with serial interface for testing flash memories
US8000519B1 (en) * 2007-04-04 2011-08-16 Xilinx, Inc. Method of metal pattern inspection verification
KR100892262B1 (ko) * 2007-06-27 2009-04-09 세크론 주식회사 프로빙 검사장치 가동률 산출 시스템 및 이를 이용한 산출방법
JP4335961B1 (ja) * 2008-09-01 2009-09-30 Ｎｅｃエレクトロニクス株式会社 テスト回路
KR101202020B1 (ko) * 2008-11-14 2012-11-16 한국전자통신연구원 웨이퍼 수준의 집적회로 칩 조정 시스템 및 집적회로 칩 조정 방법
US8059478B2 (en) * 2008-12-04 2011-11-15 Kovio, Inc. Low cost testing and sorting for integrated circuits
US9064716B2 (en) * 2009-09-30 2015-06-23 Virtium Technology, Inc. Stacking devices at finished package level
US9002673B2 (en) * 2010-06-16 2015-04-07 Broadcom Corporation Simultaneous testing of semiconductor components on a wafer
US8952712B2 (en) 2010-06-16 2015-02-10 Broadcom Corporation Tagging of functional blocks of a semiconductor component on a wafer
US20120159274A1 (en) * 2010-12-21 2012-06-21 Balakrishnan Kedarnath J Apparatus to facilitate built-in self-test data collection
US20140088911A1 (en) * 2011-05-29 2014-03-27 Cigol Digital Systems Ltd. VLSI Circuit Verification
US9304163B2 (en) 2013-11-07 2016-04-05 Qualcomm Incorporated Methodology for testing integrated circuits
US10451653B2 (en) * 2014-12-19 2019-10-22 Teradyne, Inc. Controlling a per-pin measurement unit
US9824774B2 (en) 2015-03-16 2017-11-21 Nxp Usa, Inc. Magnetic field programming of electronic devices on a wafer
US9607911B2 (en) 2015-03-16 2017-03-28 Nxp Usa, Inc. Optical programming of electronic devices on a wafer
EP3252487A1 (en) * 2016-06-01 2017-12-06 NXP USA, Inc. Wafer-level programming and testing of electronic devices
US10429441B2 (en) * 2017-05-24 2019-10-01 Qualcomm Incorporated Efficient test architecture for multi-die chips
GB2581861B (en) * 2018-09-14 2022-10-05 Sino Ic Tech Co Ltd IC Test Information Management System Based on Industrial Internet
TWI773301B (zh) * 2021-05-07 2022-08-01 華邦電子股份有限公司 半導體晶圓與多晶片的並行測試方法
CN119137730A (zh) * 2022-05-23 2024-12-13 美商艾德亚半导体接合科技有限公司 用于结合结构的测试元件
CN114880184B (zh) * 2022-05-23 2023-09-08 山东三未信安信息科技有限公司 一种批量检测pci密码卡的方法及系统
US12393544B2 (en) * 2023-04-18 2025-08-19 Qualcomm Incorporated Dynamic die-to-die serial lane configuration

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JPH04207051A (ja) * 1990-11-30 1992-07-29 Fujitsu Ltd ウエハスケールインテグレーションデバイスの製造方法
JPH0697244A (ja) * 1992-07-17 1994-04-08 Internatl Business Mach Corp <Ibm> 集積回路チップの相互接続検査方法
JPH08107185A (ja) * 1994-10-05 1996-04-23 Nec Corp 半導体記憶装置
JPH0955411A (ja) * 1995-08-17 1997-02-25 Fujitsu Ltd 半導体ウェハの試験方法および半導体ウェハ
JP2001084794A (ja) * 1999-07-12 2001-03-30 Samsung Electronics Co Ltd 交流ストレスのバーンインテスト可能な集積回路及びこれを用いたテスト方法
JP2002055145A (ja) * 2000-06-16 2002-02-20 Agilent Technol Inc マルチポート試験機能を持つ集積回路テスタおよび被験デバイスの試験方法
JP2002090414A (ja) * 2000-09-14 2002-03-27 Advantest Corp 半導体試験装置
WO2002037504A1 (en) * 2000-11-06 2002-05-10 Advantest Corporation Memory defect remedy analyzing method and memory test instrument
JP2002538465A (ja) * 1999-03-01 2002-11-12 フォームファクター，インコーポレイテッド 単一のテスターチャンネルを使用して複数のデバイスの同時テストを行うための分散型インターフェース

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JP2000100880A (ja) 1998-09-22 2000-04-07 Sharp Corp 半導体集積回路のテスト装置
US6321320B1 (en) 1998-10-30 2001-11-20 Hewlett-Packard Company Flexible and programmable BIST engine for on-chip memory array testing and characterization
US6593762B1 (en) * 1999-11-01 2003-07-15 Agilent Technologies, Inc. Apparatus for testing electronic components
US7113902B2 (en) * 2000-03-02 2006-09-26 Texas Instruments Incorporated Data processing condition detector with table lookup
US6717429B2 (en) * 2000-06-30 2004-04-06 Texas Instruments Incorporated IC having comparator inputs connected to core circuitry and output pad
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US6710616B1 (en) * 2001-07-30 2004-03-23 Lsi Logic Corporation Wafer level dynamic burn-in
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JPH04207051A (ja) * 1990-11-30 1992-07-29 Fujitsu Ltd ウエハスケールインテグレーションデバイスの製造方法
JPH0697244A (ja) * 1992-07-17 1994-04-08 Internatl Business Mach Corp <Ibm> 集積回路チップの相互接続検査方法
JPH08107185A (ja) * 1994-10-05 1996-04-23 Nec Corp 半導体記憶装置
JPH0955411A (ja) * 1995-08-17 1997-02-25 Fujitsu Ltd 半導体ウェハの試験方法および半導体ウェハ
JP2002538465A (ja) * 1999-03-01 2002-11-12 フォームファクター，インコーポレイテッド 単一のテスターチャンネルを使用して複数のデバイスの同時テストを行うための分散型インターフェース
JP2001084794A (ja) * 1999-07-12 2001-03-30 Samsung Electronics Co Ltd 交流ストレスのバーンインテスト可能な集積回路及びこれを用いたテスト方法
JP2002055145A (ja) * 2000-06-16 2002-02-20 Agilent Technol Inc マルチポート試験機能を持つ集積回路テスタおよび被験デバイスの試験方法
JP2002090414A (ja) * 2000-09-14 2002-03-27 Advantest Corp 半導体試験装置
WO2002037504A1 (en) * 2000-11-06 2002-05-10 Advantest Corporation Memory defect remedy analyzing method and memory test instrument

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5269896B2 (ja) * 2008-06-02 2013-08-21 株式会社アドバンテスト 試験用ウエハユニット、および、試験システム

Also Published As

Publication number Publication date
GB2391706B (en) 2005-12-28
US7412639B2 (en) 2008-08-12
GB2391706A (en) 2004-02-11
GB0311342D0 (en) 2003-06-25
US20030221152A1 (en) 2003-11-27

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