TW462103B - Wafer testing device and method - Google Patents

Wafer testing device and method Download PDF

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Publication number
TW462103B
TW462103B TW087104656A TW87104656A TW462103B TW 462103 B TW462103 B TW 462103B TW 087104656 A TW087104656 A TW 087104656A TW 87104656 A TW87104656 A TW 87104656A TW 462103 B TW462103 B TW 462103B
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TW
Taiwan
Prior art keywords
wafer
test
burn
patent application
scope
Prior art date
Application number
TW087104656A
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Chinese (zh)
Inventor
Fu-Jia Shiu
Original Assignee
Shiu Fu Jia
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Publication date
Application filed by Shiu Fu Jia filed Critical Shiu Fu Jia
Priority to TW087104656A priority Critical patent/TW462103B/en
Priority to US09/275,503 priority patent/US6265888B1/en
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Publication of TW462103B publication Critical patent/TW462103B/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2862—Chambers or ovens; Tanks

Abstract

The present invention discloses a wafer fixing device and its testing method. The present invention includes a wafer probe card (WPC). The WPC can be used to simultaneously test a plurality of chips on a wafer. In addition, the present invention can heat and test the chip speed in the wafer stage without waiting for the chip to be packaged into a product for performing the heating test. The WPC of the present invention produces a probe tip manufactured by wafer manufacturing technique to couple to the wafer under test, and contact points manufactured by printed circuit board technique to couple to the IC tester and/or burn-in system. The WPC also produces the probe tip by mask set same as the one for manufacturing the wafer. The technique disclosed by the present invention can be used in wafer scale screening test and/or burn-in test. Therefore, the present invention can reduce the burn-in test space and replace the conventional burn-in test of packaged product by the wafer burn-in test. In addition, the present invention can use wafer scale test to decrease the load and unload procedures of burn-in test by wafer scale test, thereby reducing the testing cost and packaging cost for those packaged product which can not pass the burn-in test and can not be repaired, and increasing the productivity by repairing the burn-in products.

Description

4 621 03 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（1 ) 發明領域 本發明係關於半導體記憶體裝置之測試裝置及方法，尤 其係關於半導體動態隨機存取記憶體（DRAM)及靜態隨機 存取記憶體（SRAM)及嵌入式裝置（Embeded Devices)(如 S ystem on Chip及Graphic with DRAM)晶圓之測試裝置及其 方法。 發明背景 D R A Μ及S R A Μ記憶體晶片必須經過多次之測試方能 確保其品質，並且必須在封裝後經老化測試以符可靠性之 要求。 一般而言，晶圓篩選測試即可篩選出晶圓製造時所發生 之缺失°如果晶片上有冗餘（redundancy)電路時，則第 二次晶圓篩選測試即用以篩選出經修復後之不良品。在封 裝程序後，前置老化測試（p r e b u r η - i η )，即開路/短路 測試，用以篩選封裝之不良品，例如短路或漏電流等會降 低老化效應之缺失。然後後續老化測試（ρ 0 s t b U r η _ i n 再用以篩選出老化測試之不良品及/或在高溫測試速度。 最後’在另一封裝程序（如蓋印）後再加以測試以確保常溫 運作下之可靠性。因此，一個D R A Μ或S R A Μ之成品須 約％4到5」^之測試且歷時—4兔7免少一時之老化測試時間以確 保其品質及可靠性。 現今高密度之記憶體（如6 4 / 2 5 6 M b i t e s )之測試時間 較先前之記憶體（如1/4/16 Mbites)爲長且60-80%之 良品係經修復過的。習用之探針技術由於探針頭佈局之限 52044. DOC\HVC -4- 本纸伕尺度適用中國國家螵准（CNS ·Μ4Λ咚/ 2i0/297公釐） (請先閱讀.背面之注意事項再填寫太f ) 装！ 訂 Α7 五、發明説明（2 ) ^ 制及昂貴的晶圓探針系統之限制，一般只能同時測試Μ 印片此外，由於習用之探針頭較長，會有阻抗匹配不 良（問減’因此典法測試高速之產品亦無法在高溫下測試 速度。故習用裂置只能在後續老化測試時測試速度以筛選 出不良品。再者’習用老化測試技術係用封裝後之成品作 測4，因此，需要大量昂貴的老化測試系統及昴貴的老化 測試插座及老化測試板，此外，還需將封裝後之成品自管 内卸載至老化測試板及自老化測試板再裝載至管内之程 序。在a用封裝/測試程序中，經老化測試後，約有1 % _ 3 %之成品係爲可修復的，然而，由於這些成品業已封裳 几畢，故供法再行修復，因此，整個生產成本因而提高。 發明之簡要説明 爲兄服習知技藝之缺點，本發明揭示一種創新之晶圓探 針板及其轉接板’以進行晶圓級測試及晶圓老化測試，進 而減少老化測試之次數及裝載/卸載之程序。 本發明I一目的在於提供—種記憶體裝置之晶圓級測試 技術以m ^。 經濟部中央標準局員工消費合作社印製 本發明t另一目的在於提供—種在記憶體裝置測試 時之測試技術以減少測試成本3 本發明 < 再一目的在於提供一種價廉之晶圓測試技術以 節省昂貴之老化測試系統及老化測試板。 本發明之再—目的在於提供—種無需裝載/卸載封裝成 品之老化測試步驟之方法’以簡化測試流程。 本發明之再一目的在於提供一種無需老化測試插座即可 52044, DOC'HYC ^ 本紙張尺度逋用子國1!家$草（CNS ) Λ4^格；W7公旖） •6 21 〇 五 、發明説明（ Α7 Β7 經濟部中央標準局員工消費合作社印掣 進行老化測試之技術。 本發明之再—目的在於提供一種完全無需前置老 步嫌之老化測試技術。 4 本發明之再—目的在於提供—種可在高溫高速 圓測試之技術。 丁叫 ::明之再—目的在於提供—種無需昂貴之晶圓探測系 統即可進行晶圓篩選測試之技術。 ·、 本發明之再—目的在於提供一種可利用1C打線墊上之 kelvln電路進行晶圓篩選測試之技術。 星_式之簡單諸. 爲説月本發明之其他目的及其優點，現以下列較佳實# 例配合附圖之説明敘述如後，其+ ^ 圖1所示爲本發明所揭示之整個晶圓探針板系統之平面 圖； 圖2 a及2 b所不爲本發明所揭示之晶圓探針板之局部俯 視圖及仰視圖；及 圖所示爲本發明所揭示之晶圓探針板之局部剖視圖。 發明之詳細説明 /閲圖1，圖1揭示了本發明所請之晶圓探針板系 、-先本發明王要包含—下夾具21及一上夹具20。其中下 夾具2 1係用以固定—待測晶圓丨6於其上表面。該待測晶 圓1 6 (如記憶體裝置之晶圓）係利用下夾具2 ι中之眞空吸 孔17來吸持及平坦化。此外，下夾具川更包含一加熱器 1 9及—感測器】8，其中該加熱器I 9用以加熱該待測晶圓4 621 03 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (1) Field of the Invention The present invention relates to a test device and method for semiconductor memory devices, and more particularly to semiconductor dynamic random access memory (DRAM ) And static random access memory (SRAM) and embedded device (Embeded Devices) (such as System on Chip and Graphic with DRAM) wafer test devices and methods. BACKGROUND OF THE INVENTION D RAM and S RAM memory chips must be tested several times to ensure their quality, and they must undergo aging tests after packaging to meet reliability requirements. In general, wafer screening tests can screen out defects that occur during wafer manufacturing. If there are redundant circuits on the wafer, the second wafer screening test is used to screen out the repaired ones. Defective. After the packaging process, the pre-aging test (p r e b u r η-i η), which is an open / short test, is used to screen out defective packages, such as short circuits or leakage currents, which will reduce the lack of aging effects. Then follow-up burn-in test (ρ 0 stb U r η _ in is used to screen out the bad products of burn-in test and / or test speed at high temperature. Finally, test again after another packaging process (such as stamping) to ensure normal temperature Reliability under operation. Therefore, the finished product of a DRA M or SRA M must be tested at a rate of about 4 to 5 "^ and lasts-4 rabbits and 7 free of aging test time to ensure its quality and reliability. Today's high density The test time of the memory (such as 6 4/2 5 6 M bites) is longer than the previous memory (such as 1/4/16 Mbites) and 60-80% of the good strains have been repaired. Used probes Due to the limitation of the probe head layout 52044. DOC \ HVC -4- The standard of this paper is applicable to China National Standards (CNS · M4Λ 2 / 2i0 / 297mm) (Please read first. Note on the back and then fill in too f ) Assembly! Order A7 V. Description of the invention (2) ^ Due to the limitation of manufacturing and expensive wafer probe system, generally only M print can be tested at the same time. In addition, because the conventional probe head is long, there will be poor impedance matching ( Ask and subtract 'so code test high-speed products cannot be tested at high temperatures Therefore, conventional cracking can only test the speed to screen out defective products during subsequent burn-in tests. Furthermore, the conventional burn-in test technology uses packaged finished products for testing4. Therefore, a large number of expensive burn-in test systems and expensive Burn-in test socket and burn-in test board. In addition, the packaged product must be unloaded from the tube to the burn-in test board and the burn-in test board and reloaded into the tube. In the package / test procedure for a, after burn-in test About 1% _ 3% of the finished products are repairable. However, because these finished products have been sealed for several times, they are repaired by law, so the overall production cost is increased. Brief description of the invention Knowing the shortcomings of the art, the present invention discloses an innovative wafer probe card and its adapter board to perform wafer-level tests and wafer burn-in tests, thereby reducing the number of burn-in tests and loading / unloading procedures. This invention I One purpose is to provide a wafer-level test technology for memory devices in m ^. The invention is printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs and another purpose is to provide- A test technology for testing a memory device to reduce test costs 3 The present invention < another object is to provide an inexpensive wafer test technology to save expensive burn-in test systems and burn-in test boards. The purpose is to provide a method of aging test steps without loading / unloading the packaged product to simplify the test process. Another object of the present invention is to provide a test socket without aging test. 52044, DOC'HYC 1! Home grass (CNS) Λ4 ^ grid; W7 public money) • 6 21 05. Invention Description (Α7 Β7 Technology of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs printed the technology for aging test. Another object of the present invention is to provide an aging test technology that does not require premature aging. 4 Another object of the present invention is to provide a technique which can perform circle test at high temperature and high speed. Ding Jiao :: Mingzhi Zai-The purpose is to provide-a technology that can perform wafer screening test without expensive wafer detection system. · Another aspect of the present invention is to provide a technology for performing wafer screening test using a kelvln circuit on a 1C wire bonding pad. The stars are simple. In order to explain the other purposes and advantages of the present invention, the following better examples are described below with the description of the drawings as follows. Its + ^ Figure 1 shows the entire disclosure of the present invention Plan view of the wafer probe card system; Figures 2a and 2b are partial top and bottom views of the wafer probe card disclosed in the present invention; and the figure shows the wafer probe card disclosed in the present invention A partial cross-sectional view. Detailed description of the invention / See FIG. 1, which discloses the wafer probe card system requested by the present invention. First, the present invention includes the lower fixture 21 and the upper fixture 20. The lower clamp 21 is used to fix the wafer to be tested on its upper surface. The wafer 16 to be measured (such as a wafer of a memory device) is held and flattened by using a hollow suction hole 17 in the lower jig 2m. In addition, the lower fixture includes a heater 19 and a sensor] 8, wherein the heater I 9 is used to heat the wafer to be tested.

52044.DOC\HYC -6- 本紙悵尺度適用中国國京崠洗CNS]A^Tii；'( 210X29'^-4 )" (碕先聞請背面之注念事項再填寫本1) 裝，i ------訂------ -III - - -II _ I 二· 經濟部中央標準局貝工消費合作社印災 4 6 21 0 A7 -----B7 五'發明説明（4 ) ^ 16，而該感測器18則用以控制加熱溫度至所設定之溫 度。晶圓探針板1 3之上表面係利用印刷雷路板之技術形 成星—数.個接點（如圖2 a所示）及線路（未顯示）以耦接至〜 轉接板12，該轉接板12可轉接至測試機之負載板（丨 b 〇 a r d)或爲老化測試板（1 1 )，而該等接點及線路之材料 係可爲B T或銅等材料。此外，該晶圓探針板丄3之下表面 係利用晶圓製造技術形成屋數個探針頭（ρΓ〇“ tips)32(如圖2b及圖3所示），而探針頭32之材料則爲轉 或及組合物，其中每個信號接點3 3間均有接地而3 1以防 止5虎間之互相干擾°該晶圓探針板1 3更包含一定位孔 1 5以利於該晶圓探針板I 3放置於該上夹具2 〇時之定位。 遠上夾具20亦更包含一組扣件14，以將該下夾具2】及該 上夾具2 0扣持結合在一起。該上夹具2 〇則利用一眞空吸 孔2 2以在上夾具2 〇及下夾具2 1結合後固定及平坦待測晶 圓16於r夾具21之表面。此即完成本發明所請之固定待 測晶圓之裝置。該下夹具2 1更包含複數個緩衝裝置（如彈 簧）2 3以在該下夹具2 1與上夹具2 0結合時作緩衝之用， 以避免損壞該探針頭3 2或該待測晶圓1 6 =在該上夾具2 〇 及該下夹具2 1結合後，即可將結合後之裝置與該轉接板 1 2耦接，該轉接板1 2再與一測試機1 1耦接以進行晶圓之 測試。 本發明所揭示之創新固定待測晶圓之裝置可用以在高溫 高速下測試待測晶圓，並大幅節省測試成本及步驟，其測 試方法如下所述： 52044.DOCHYC -7， 本祇張尺度適用中賴家_格·，：j〇:；^7公梦] "—- (椅先閱讀背鬲之注意事項再填寫本頁) 裝 6 1 〇3 A? B7 五 、發明説明（5 ) 首先在將待測晶圓置入本發明太 後， "青之固定待測晶圓裝置 ⑻利用加熱器加熱—待測晶圓以—丄 ⑹力古：®古 '备ΊΓ 》 行高溫老化測試： 仰在问植同速下進行晶圓級測試； (C)對不良之晶片進行冗餘修復； (d) 對修復後之晶片再進行篩選； (e) 組裝晶片爲封裝Ϊ C ; ⑴將該封裝I C蓋印標示；及 ⑻在常溫下做最後測試。 本發明所揭示之測試方法相較於 , *知疋測試万法可至少 名略4個步驟，因此可大幅減少測种昧 Μ、 又愒成/剧試時間及測試成本。其 迅^比較如下表所士 : 知之測試方法 ⑻在常溫下篩選晶圓（每次12 加熱器加熱一待測 請先閲讀背面之注意事項再填寫本頁 在------訂--- 經濟部中央標準局員工消費合作社印製 個） (b) 對不良之晶片進行冗試； (c) 對修復後之晶片再進行篩選； (d) 組裝晶片爲封裝I匚； ⑹前置老化測試（或開路/短路 測試）： ⑴老化測試裝裁； ⑻元件老化測試： ⑸老化測試後卸載； ⑴向溫下速度gjg測試；52044.DOC \ HYC -6- The size of this paper is suitable for China ’s National Beijing Washing CNS] A ^ Tii; '(210X29' ^-4) " (碕 Please read the notes on the back before filling in this 1). i ------ Order ------ -III---II _ I II. Disaster printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 6 21 0 A7 ----- B7 Five 'invention description (4) ^ 16, and the sensor 18 is used to control the heating temperature to a set temperature. The top surface of the wafer probe board 1 3 is formed with printed circuit boards using star technology. Several contacts (as shown in FIG. 2 a) and lines (not shown) are coupled to the ~ adapter board 12. The adapter board 12 can be transferred to a load board (bold) of the testing machine or an aging test board (1 1), and the materials of the contacts and lines can be BT or copper. In addition, the lower surface of the wafer probe board 丄 3 is formed with a plurality of probe heads (ρΓ〇 “tips) 32 (as shown in FIG. 2b and FIG. 3) using wafer manufacturing technology. The material is an OR combination, where each of the signal contacts 3 and 3 are grounded and 3 1 to prevent mutual interference between 5 tigers. The wafer probe card 1 3 also includes a positioning hole 15 to facilitate The wafer probe card I 3 is positioned at the position of the upper clamp 20. The far upper clamp 20 also includes a set of fasteners 14 to hold the lower clamp 2] and the upper clamp 20 together. The upper jig 20 uses an empty suction hole 22 to fix and flatten the surface of the wafer 16 to be tested on the surface of the r jig 21 after the upper jig 20 and the lower jig 21 are combined. This completes the request of the present invention. Device for fixing the wafer to be tested. The lower fixture 21 further includes a plurality of buffer devices (such as springs) 2 3 for buffering when the lower fixture 21 is combined with the upper fixture 20 to avoid damaging the probe. Head 3 2 or the wafer under test 16 = after the upper fixture 2 0 and the lower fixture 21 are combined, the combined device can be coupled to the adapter board 12 and the transfer The connection board 12 is further coupled to a tester 11 for wafer testing. The innovative device for fixing the wafer to be tested disclosed in the present invention can be used to test the wafer to be tested at high temperature and speed, and greatly saves the test cost. And steps, and its test method is as follows: 52044.DOCHYC -7, this sheet scale is applicable to Lai Jia_Ge · ,: j〇:; ^ 7 公 梦] " —- (note that the chair reads the back first Please fill in this page again) Install 6 1 〇3 A? B7 V. Description of the invention (5) First, after the wafer to be tested is placed in the invention, " Qingzhi's fixed wafer to be tested device is heated by a heater— The wafers to be tested are subjected to high-temperature aging test: 古 古: ® 古 '备 ΊΓ ": Wafer-level testing is performed at the same speed as the ask plant; (C) Redundant repair of bad wafers; (d) Screen the repaired wafer again; (e) Assemble the wafer as a package Ϊ C; 盖 stamp the package IC; and ⑻ do the final test at normal temperature. Compared with the test method disclosed in the present invention, The test method can be at least 4 steps in name, so it can greatly reduce the number of tests, and the test / play test. Time and test cost. The comparison is as follows: Known test methods: Screen wafers at room temperature (12 heaters each time to heat one for testing, please read the precautions on the back before filling out this page on ---- --Order --- Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (b) Redundant tests of defective wafers; (c) Screening of repaired wafers; (d) Assembly of wafers into packages I 匚⑹ Pre-aging test (or open / short-circuit test): ⑴Aging test setup; ⑻Component aging test: 卸载 Unload after aging test; 速度 Speed gjg test at temperature;

52044,DOCMIYC 本紙乐尺度適用中國國家標藥7~^ 晶圓以進行高溫老化測 試； (b)在轰溫高速.下進行晶圓 級測試； ⑹對不良之晶片進行冗餘 —修復； ⑻對修復後之晶片再進行 篩選； ⑹组裝晶片爲封裝I C ; ⑴將該封裝I C蓋印標示 -8- ^規格（2i0x 公趁 462103 A 7 ____B7 五、發明説明（6 ) ⑴將該封裝1C蓋印標示；及 —----- 及 (k)在常溫下做最後測試。 ⑻在常溫下做最後測試。 本發明首揭一種晶圓固定装置及其測試方法’其可減少 老化測試空間並以晶圓老化測試取代習知之成品封裝之老 化測試。此外，本發明可藉由晶圓級測試減少老化測試之 1載（load)及卸載（unload)之程序以降低測試成衣並節省 封裝後未通過老化測試之成品無法修復之封裝成本。因 此，本發明深具可專利性。 唯上述實施例僅爲説明本發明之原理及其功效，而非限 制本發明’因此，習於此藝之人士對上述實施例所做之修 改及變化仍不達背本發明之精神^本發明之權限應如後述 之申請專利範園所列。 (对先閱讀背面之注意事項再填寫本頁 n^i· ί- - -- 1 - 裝 訂 經濟部中央標隼局員工消費合作社印製52044, DOCMIYC The paper scale is suitable for 7 ~ ^ wafers of China's national standard for high-temperature aging test; (b) Wafer-level test at high temperature and high speed; 冗余 Redundant-repair of bad wafers; ⑻ The repaired wafers are then screened; ⑹ the assembled wafer is a packaged IC; 盖 the packaged IC is stamped with -8- ^ specifications (2i0x publicly available 462103 A 7 ____B7 V. Description of the invention (6) ⑴ Cover the package 1C And (k) do the final test at normal temperature. 做 do the final test at normal temperature. The present invention first discloses a wafer fixing device and its test method, which can reduce the aging test space and The wafer burn-in test is used to replace the conventional burn-in test of the finished package. In addition, the present invention can reduce the load and unload procedures of the burn-in test by wafer-level test to reduce the test clothing and save the unpackaged The packaging cost of the finished product that can pass the aging test cannot be repaired. Therefore, the present invention is highly patentable. However, the above embodiments are only for explaining the principle and effect of the present invention, and not for limiting the present invention. Modifications and changes made by people to the above-mentioned embodiments still do not meet the spirit of the present invention ^ The authority of the present invention should be listed in the patent application park mentioned later. (Please read the precautions on the back before filling in this page n ^ i · Ί---1-Binding Printed by Staff Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs

52044. DODHYC 本纸張尺度適用士 標生/ cns )52044. DODHYC This paper is suitable for standard papers / cns)

Claims (1)

462彳〇3 A8 B8 CS D8 經濟部中央標隼局貝工消費合作社印策 、申請專利範圍 1.—種固定待測晶圓之裝置，包含： 具’用以固定一政_ 圓於其上表面，該下夾具 包含一H暴，用以加熱該待測晶圓；及 — ，用以固定一AUt就板，該晶圓探針板之上 表面設有！墓個接^及/或線路以耦接至一棘接板及下表 面設有農農_個jOlil Θ盡接至該待測晶圓。 2-如申請專利範圍第1項之裝置，其中該下夾具更包含一^ ’以吸持該待測晶圓。 3.·如中請專利範圍第1項之裝置，其中該下夹具更包含一^ ，以控制該加熱器之溫度。 4，如申請專利範園第1項之裝置，其中該晶圓探針板之該上 表面之複數個接點及/或線路係以^J1電路极技術形成。 5. 如申請專利範圍第1項之裝置，其中該晶圓探針板之下表 面之複數個iH覌係以技術形成。 6. 如申請專利範圍第4項之裝置，其中該晶圓探針板之上表 面之複數個接點及/或線路之材料爲銅。 7. 如申請專利範圍第4項之装置’其中該晶圓探針板之上表 面之複數個接點及/或線路之材料爲Β τ。 8. 如申請專利範圍第5之裝置，其中該晶圓探針板之下表面 之複數個探針頭之材料爲鎢。 9. 如申诸專利範圍第1項之裝置’其中該轉接板可轉接至測 試機之負載板。 10. 如申請專利範圍第1項之裝£ ’其中該轉接板可轉接至耐 久測試板。 52044.DOOHYC -10- 本紙張尺度逋用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閣讀背面之注意事碩再填寫本頁) ¾.. 、1' 462103 A8 B8 C8 D8 六、申請專利範圍 ^ 11. 如申請專利範圍第丨項之裝置，其中該上夾具更包含一組 扣件以扣持該下夾具。 12. 如申4專利範園第i項之裝置，其中該晶圓探針板更包含 定位孔以定位該晶圓探針板於該晶圓上。 13. 如申請專利範圍第丨項之裝置，其中該上夹具更包含一眞 空吸孔以吸持該晶圓於該下夹具。 14如申請專利範園第丨項之裝置，其中該下夹具更包含複數 個緩衝裝置。 15，一種晶圓測試之方法，包含下列之步驟： ⑻利用_奴| _蓋加熱一待測晶圓以進行ϋ老二化測試； ⑸在五.溫_ .愚益下進行晶圓級測試； (c) 對不良之晶片進行冗餘修德； (d) 對後之晶片再進行飾選； ⑹組裝晶片爲封裝I c ; (f)將該封裝I C 1印德示:及 ⑻在常溫下做最後測試。 16. 如申請專利範圍第1 5項之方法，其中該晶圓爲記憶體裝 置之晶圓。 17. 如申清專利範圍第1 5項之方法，其中該晶圓爲含記憶體 之特殊設計晶圓。 • 18. —種晶圓探針板，包含： -政有jlU接點及/气5接至一轉接板之上表 面：及 "设有複蓋塑蓋直.頭-以耦接至一待測晶圓之下表面。 52〇44.D〇CvHYC βι ι 本紙伕尺度適用中國國家標準（CNS ) A4規格（210 X 297公庚） I u I fn - - n I - m HI _ ___T -3 . -va ,(请先閱讀背面之注意事項存填寫本頁) 經濟部尹央樣準局員工消費合作社印衆462 彳 〇3 A8 B8 CS D8 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, and applied for patent scope 1. A device for fixing wafers to be tested, including: with 'to fix a government _ round on it On the surface, the lower jig contains an H burst for heating the wafer to be tested; and-for fixing an AUT plate, and the upper surface of the wafer probe card is provided! Tombs and / or lines are coupled to a ratchet plate and a farmer and a jOlil Θ are connected to the wafer under test. 2- The device according to item 1 of the patent application scope, wherein the lower jig further includes a ^ 'to hold the wafer to be tested. 3. The device in item 1 of the patent scope, wherein the lower fixture further includes a ^ to control the temperature of the heater. 4. The device according to item 1 of the patent application park, wherein the plurality of contacts and / or lines on the upper surface of the wafer probe card are formed by the ^ J1 circuit pole technology. 5. The device according to item 1 of the scope of patent application, wherein a plurality of iHs on the surface below the wafer probe card are formed by technology. 6. For the device under the scope of patent application, the material of the plurality of contacts and / or lines on the surface of the wafer probe card is copper. 7. The device according to item 4 of the scope of patent application, wherein the material of the plurality of contacts and / or lines on the surface of the wafer probe card is Bτ. 8. For the device in the fifth scope of the patent application, the material of the plurality of probe heads on the lower surface of the wafer probe card is tungsten. 9. For the device according to claim 1 of the patent scope, wherein the adapter plate can be transferred to the load plate of the test machine. 10. In the case of the first patent application, the adapter board can be transferred to the durability test board. 52044.DOOHYC -10- This paper size adopts Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the cautions on the back before filling out this page) ¾ .., 1 '462103 A8 B8 C8 D8 6. Scope of patent application ^ 11. For the device of scope 丨 of the patent application, the upper jig further includes a set of fasteners to hold the lower jig. 12. The device of item i of the patent claim 4, wherein the wafer probe card further includes a positioning hole to position the wafer probe card on the wafer. 13. The device according to item 丨 of the patent application, wherein the upper jig further includes an empty suction hole to hold the wafer in the lower jig. 14 The device according to item 丨 of the patent application park, wherein the lower jig further includes a plurality of buffer devices. 15. A method for wafer testing, including the following steps: ⑻Using _ slave | _ cover to heat a wafer under test for ϋolder second test; 进行 Wafer-level test at five temperatures. (C) Redundant morality of defective wafers; (d) Re-selection of subsequent wafers; ⑹Assembly the chip to package I c; (f) Print the package IC 1 with German marks: and ⑻ at room temperature Do the final test. 16. The method according to item 15 of the patent application scope, wherein the wafer is a wafer of a memory device. 17. The method of claim 15 of the patent scope, wherein the wafer is a specially designed wafer containing memory. • 18. —A kind of wafer prober board, including:-a government jlU contact and / / 5 connected to the upper surface of an adapter board: and " covered with a plastic cover straight. Head-to be coupled to A lower surface of the wafer to be tested. 52〇44.D〇CvHYC βι ι The size of this paper is applicable to Chinese National Standard (CNS) A4 (210 X 297 hectares) I u I fn--n I-m HI _ ___T -3. -Va, (please first (Please read the notes on the back and fill in this page) Yin Yang Sample Procurement Bureau of the Ministry of Economic Affairs
TW087104656A 1998-03-27 1998-03-27 Wafer testing device and method TW462103B (en)

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US09/275,503 US6265888B1 (en) 1998-03-27 1999-03-24 Wafer probe card

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