JP2002334973A5 - - Google Patents

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Publication number
JP2002334973A5
JP2002334973A5 JP2002060538A JP2002060538A JP2002334973A5 JP 2002334973 A5 JP2002334973 A5 JP 2002334973A5 JP 2002060538 A JP2002060538 A JP 2002060538A JP 2002060538 A JP2002060538 A JP 2002060538A JP 2002334973 A5 JP2002334973 A5 JP 2002334973A5
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JP
Japan
Prior art keywords
trench
ferromagnetic
coating layer
depositing
sidewalls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002060538A
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English (en)
Japanese (ja)
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JP2002334973A (ja
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Publication date
Priority claimed from US09/802,650 external-priority patent/US6475812B2/en
Application filed filed Critical
Publication of JP2002334973A publication Critical patent/JP2002334973A/ja
Publication of JP2002334973A5 publication Critical patent/JP2002334973A5/ja
Pending legal-status Critical Current

Links

JP2002060538A 2001-03-09 2002-03-06 上部導体にクラッド層を形成するための方法 Pending JP2002334973A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/802650 2001-03-09
US09/802,650 US6475812B2 (en) 2001-03-09 2001-03-09 Method for fabricating cladding layer in top conductor

Publications (2)

Publication Number Publication Date
JP2002334973A JP2002334973A (ja) 2002-11-22
JP2002334973A5 true JP2002334973A5 (https=) 2005-04-07

Family

ID=25184320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002060538A Pending JP2002334973A (ja) 2001-03-09 2002-03-06 上部導体にクラッド層を形成するための方法

Country Status (8)

Country Link
US (1) US6475812B2 (https=)
EP (1) EP1239489B1 (https=)
JP (1) JP2002334973A (https=)
KR (1) KR100855573B1 (https=)
CN (1) CN1374691A (https=)
DE (1) DE60201036T2 (https=)
HK (1) HK1049067A1 (https=)
TW (1) TW513803B (https=)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10043947A1 (de) * 2000-09-06 2002-04-04 Infineon Technologies Ag Integrierte Schaltungsanordnung
US6555858B1 (en) 2000-11-15 2003-04-29 Motorola, Inc. Self-aligned magnetic clad write line and its method of formation
US6413788B1 (en) * 2001-02-28 2002-07-02 Micron Technology, Inc. Keepers for MRAM electrodes
US6545906B1 (en) 2001-10-16 2003-04-08 Motorola, Inc. Method of writing to scalable magnetoresistance random access memory element
US6720597B2 (en) * 2001-11-13 2004-04-13 Motorola, Inc. Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers
US6661688B2 (en) * 2001-12-05 2003-12-09 Hewlett-Packard Development Company, L.P. Method and article for concentrating fields at sense layers
US6525957B1 (en) * 2001-12-21 2003-02-25 Motorola, Inc. Magnetic memory cell having magnetic flux wrapping around a bit line and method of manufacturing thereof
US6780653B2 (en) * 2002-06-06 2004-08-24 Micron Technology, Inc. Methods of forming magnetoresistive memory device assemblies
US7095646B2 (en) 2002-07-17 2006-08-22 Freescale Semiconductor, Inc. Multi-state magnetoresistance random access cell with improved memory storage density
JP2006134363A (ja) 2002-07-29 2006-05-25 Nec Corp 磁気ランダムアクセスメモリ
US6770491B2 (en) * 2002-08-07 2004-08-03 Micron Technology, Inc. Magnetoresistive memory and method of manufacturing the same
US6914805B2 (en) * 2002-08-21 2005-07-05 Micron Technology, Inc. Method for building a magnetic keeper or flux concentrator used for writing magnetic bits on a MRAM device
KR100515053B1 (ko) * 2002-10-02 2005-09-14 삼성전자주식회사 비트라인 클램핑 전압 레벨에 대해 안정적인 독출 동작이가능한 마그네틱 메모리 장치
JP3906145B2 (ja) * 2002-11-22 2007-04-18 株式会社東芝 磁気ランダムアクセスメモリ
US7184301B2 (en) 2002-11-27 2007-02-27 Nec Corporation Magnetic memory cell and magnetic random access memory using the same
US6885074B2 (en) * 2002-11-27 2005-04-26 Freescale Semiconductor, Inc. Cladded conductor for use in a magnetoelectronics device and method for fabricating the same
US6870759B2 (en) * 2002-12-09 2005-03-22 Applied Spintronics Technology, Inc. MRAM array with segmented magnetic write lines
US6909630B2 (en) 2002-12-09 2005-06-21 Applied Spintronics Technology, Inc. MRAM memories utilizing magnetic write lines
US6909633B2 (en) 2002-12-09 2005-06-21 Applied Spintronics Technology, Inc. MRAM architecture with a flux closed data storage layer
US6943038B2 (en) * 2002-12-19 2005-09-13 Freescale Semiconductor, Inc. Method for fabricating a flux concentrating system for use in a magnetoelectronics device
US6864551B2 (en) * 2003-02-05 2005-03-08 Applied Spintronics Technology, Inc. High density and high programming efficiency MRAM design
US6812538B2 (en) 2003-02-05 2004-11-02 Applied Spintronics Technology, Inc. MRAM cells having magnetic write lines with a stable magnetic state at the end regions
US6940749B2 (en) 2003-02-24 2005-09-06 Applied Spintronics Technology, Inc. MRAM array with segmented word and bit lines
US6963500B2 (en) * 2003-03-14 2005-11-08 Applied Spintronics Technology, Inc. Magnetic tunneling junction cell array with shared reference layer for MRAM applications
US6933550B2 (en) * 2003-03-31 2005-08-23 Applied Spintronics Technology, Inc. Method and system for providing a magnetic memory having a wrapped write line
US7067866B2 (en) * 2003-03-31 2006-06-27 Applied Spintronics Technology, Inc. MRAM architecture and a method and system for fabricating MRAM memories utilizing the architecture
US6785160B1 (en) * 2003-04-29 2004-08-31 Hewlett-Packard Development Company, L.P. Method of providing stability of a magnetic memory cell
US6956763B2 (en) 2003-06-27 2005-10-18 Freescale Semiconductor, Inc. MRAM element and methods for writing the MRAM element
US6967366B2 (en) 2003-08-25 2005-11-22 Freescale Semiconductor, Inc. Magnetoresistive random access memory with reduced switching field variation
US7078239B2 (en) * 2003-09-05 2006-07-18 Micron Technology, Inc. Integrated circuit structure formed by damascene process
US6819586B1 (en) * 2003-10-24 2004-11-16 Hewlett-Packard Development Company, L.P. Thermally-assisted magnetic memory structures
US20050141148A1 (en) 2003-12-02 2005-06-30 Kabushiki Kaisha Toshiba Magnetic memory
US20050205952A1 (en) * 2004-03-19 2005-09-22 Jae-Hyun Park Magnetic random access memory cells having split sub-digit lines having cladding layers thereon and methods of fabricating the same
US6946698B1 (en) 2004-04-02 2005-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM device having low-k inter-metal dielectric
US20060039183A1 (en) * 2004-05-21 2006-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-sensing level MRAM structures
WO2005122259A1 (ja) * 2004-06-10 2005-12-22 Nec Corporation 磁気メモリ
US7221584B2 (en) * 2004-08-13 2007-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM cell having shared configuration
US7129098B2 (en) 2004-11-24 2006-10-31 Freescale Semiconductor, Inc. Reduced power magnetoresistive random access memory elements
US20130082232A1 (en) 2011-09-30 2013-04-04 Unity Semiconductor Corporation Multi Layered Conductive Metal Oxide Structures And Methods For Facilitating Enhanced Performance Characteristics Of Two Terminal Memory Cells
US7407885B2 (en) * 2005-05-11 2008-08-05 Micron Technology, Inc. Methods of forming electrically conductive plugs
KR100682950B1 (ko) * 2005-07-28 2007-02-15 삼성전자주식회사 강유전체 기록매체 및 그 제조 방법
US7738287B2 (en) * 2007-03-27 2010-06-15 Grandis, Inc. Method and system for providing field biased magnetic memory devices
JP2009283843A (ja) * 2008-05-26 2009-12-03 Renesas Technology Corp 半導体装置及びその製造方法
US7833806B2 (en) 2009-01-30 2010-11-16 Everspin Technologies, Inc. Structure and method for fabricating cladded conductive lines in magnetic memories
KR101983137B1 (ko) * 2013-03-04 2019-05-28 삼성전기주식회사 파워 인덕터 및 그 제조방법
US10403424B2 (en) 2017-06-09 2019-09-03 Texas Instruments Incorporated Method to form magnetic core for integrated magnetic devices
CN112133820A (zh) * 2019-06-25 2020-12-25 中电海康集团有限公司 Mram底电极的制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2728025B2 (ja) 1995-04-13 1998-03-18 日本電気株式会社 半導体装置の製造方法
ATE223108T1 (de) * 1995-04-24 2002-09-15 Infineon Technologies Ag Halbleiter-speichervorrichtung unter verwendung eines ferroelektrischen dielektrikums und verfahren zur herstellung
JPH09191084A (ja) * 1996-01-10 1997-07-22 Nec Corp 半導体装置及びその製造方法
US5732016A (en) * 1996-07-02 1998-03-24 Motorola Memory cell structure in a magnetic random access memory and a method for fabricating thereof
US6030877A (en) * 1997-10-06 2000-02-29 Industrial Technology Research Institute Electroless gold plating method for forming inductor structures
US5956267A (en) 1997-12-18 1999-09-21 Honeywell Inc Self-aligned wordline keeper and method of manufacture therefor
US6278165B1 (en) * 1998-06-29 2001-08-21 Kabushiki Kaisha Toshiba MIS transistor having a large driving current and method for producing the same
US5940319A (en) * 1998-08-31 1999-08-17 Motorola, Inc. Magnetic random access memory and fabricating method thereof
JP2000090658A (ja) * 1998-09-09 2000-03-31 Sanyo Electric Co Ltd 磁気メモリ素子
US6872993B1 (en) * 1999-05-25 2005-03-29 Micron Technology, Inc. Thin film memory device having local and external magnetic shielding
JP2001230468A (ja) * 2000-02-17 2001-08-24 Sharp Corp 磁気トンネル接合素子及びそれを用いた磁気メモリ
DE10106860A1 (de) * 2000-02-17 2001-08-30 Sharp Kk MTJ-Element und Magnetspeicher unter Verwendung eines solchen
US6211090B1 (en) * 2000-03-21 2001-04-03 Motorola, Inc. Method of fabricating flux concentrating layer for use with magnetoresistive random access memories
TW459374B (en) * 2000-08-30 2001-10-11 Mosel Vitelic Inc Method for forming magnetic layer of magnetic random access memory
US6555858B1 (en) * 2000-11-15 2003-04-29 Motorola, Inc. Self-aligned magnetic clad write line and its method of formation
US6413788B1 (en) * 2001-02-28 2002-07-02 Micron Technology, Inc. Keepers for MRAM electrodes

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