HK1049067A1 - 頂部導體包層的製造方法 - Google Patents

頂部導體包層的製造方法

Info

Publication number
HK1049067A1
HK1049067A1 HK03101239.6A HK03101239A HK1049067A1 HK 1049067 A1 HK1049067 A1 HK 1049067A1 HK 03101239 A HK03101239 A HK 03101239A HK 1049067 A1 HK1049067 A1 HK 1049067A1
Authority
HK
Hong Kong
Prior art keywords
cladding layer
top conductor
fabricating
fabricating cladding
conductor
Prior art date
Application number
HK03101239.6A
Other languages
English (en)
Inventor
H Nickel Janice
C Anthony Thomas
Original Assignee
惠普公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠普公司 filed Critical 惠普公司
Publication of HK1049067A1 publication Critical patent/HK1049067A1/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
HK03101239.6A 2001-03-09 2003-02-18 頂部導體包層的製造方法 HK1049067A1 (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/802,650 US6475812B2 (en) 2001-03-09 2001-03-09 Method for fabricating cladding layer in top conductor

Publications (1)

Publication Number Publication Date
HK1049067A1 true HK1049067A1 (zh) 2003-04-25

Family

ID=25184320

Family Applications (1)

Application Number Title Priority Date Filing Date
HK03101239.6A HK1049067A1 (zh) 2001-03-09 2003-02-18 頂部導體包層的製造方法

Country Status (8)

Country Link
US (1) US6475812B2 (zh)
EP (1) EP1239489B1 (zh)
JP (1) JP2002334973A (zh)
KR (1) KR100855573B1 (zh)
CN (1) CN1374691A (zh)
DE (1) DE60201036T2 (zh)
HK (1) HK1049067A1 (zh)
TW (1) TW513803B (zh)

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DE10043947A1 (de) * 2000-09-06 2002-04-04 Infineon Technologies Ag Integrierte Schaltungsanordnung
US6555858B1 (en) * 2000-11-15 2003-04-29 Motorola, Inc. Self-aligned magnetic clad write line and its method of formation
US6413788B1 (en) * 2001-02-28 2002-07-02 Micron Technology, Inc. Keepers for MRAM electrodes
US6720597B2 (en) * 2001-11-13 2004-04-13 Motorola, Inc. Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers
US6661688B2 (en) * 2001-12-05 2003-12-09 Hewlett-Packard Development Company, L.P. Method and article for concentrating fields at sense layers
US6525957B1 (en) * 2001-12-21 2003-02-25 Motorola, Inc. Magnetic memory cell having magnetic flux wrapping around a bit line and method of manufacturing thereof
US6780653B2 (en) 2002-06-06 2004-08-24 Micron Technology, Inc. Methods of forming magnetoresistive memory device assemblies
JP2006134363A (ja) * 2002-07-29 2006-05-25 Nec Corp 磁気ランダムアクセスメモリ
US6770491B2 (en) * 2002-08-07 2004-08-03 Micron Technology, Inc. Magnetoresistive memory and method of manufacturing the same
US6914805B2 (en) * 2002-08-21 2005-07-05 Micron Technology, Inc. Method for building a magnetic keeper or flux concentrator used for writing magnetic bits on a MRAM device
KR100515053B1 (ko) * 2002-10-02 2005-09-14 삼성전자주식회사 비트라인 클램핑 전압 레벨에 대해 안정적인 독출 동작이가능한 마그네틱 메모리 장치
JP3906145B2 (ja) * 2002-11-22 2007-04-18 株式会社東芝 磁気ランダムアクセスメモリ
US7184301B2 (en) 2002-11-27 2007-02-27 Nec Corporation Magnetic memory cell and magnetic random access memory using the same
US6885074B2 (en) * 2002-11-27 2005-04-26 Freescale Semiconductor, Inc. Cladded conductor for use in a magnetoelectronics device and method for fabricating the same
US6909633B2 (en) 2002-12-09 2005-06-21 Applied Spintronics Technology, Inc. MRAM architecture with a flux closed data storage layer
US6909630B2 (en) 2002-12-09 2005-06-21 Applied Spintronics Technology, Inc. MRAM memories utilizing magnetic write lines
US6870759B2 (en) * 2002-12-09 2005-03-22 Applied Spintronics Technology, Inc. MRAM array with segmented magnetic write lines
US6943038B2 (en) * 2002-12-19 2005-09-13 Freescale Semiconductor, Inc. Method for fabricating a flux concentrating system for use in a magnetoelectronics device
US6812538B2 (en) 2003-02-05 2004-11-02 Applied Spintronics Technology, Inc. MRAM cells having magnetic write lines with a stable magnetic state at the end regions
US6864551B2 (en) * 2003-02-05 2005-03-08 Applied Spintronics Technology, Inc. High density and high programming efficiency MRAM design
US6940749B2 (en) 2003-02-24 2005-09-06 Applied Spintronics Technology, Inc. MRAM array with segmented word and bit lines
US6963500B2 (en) * 2003-03-14 2005-11-08 Applied Spintronics Technology, Inc. Magnetic tunneling junction cell array with shared reference layer for MRAM applications
US6933550B2 (en) * 2003-03-31 2005-08-23 Applied Spintronics Technology, Inc. Method and system for providing a magnetic memory having a wrapped write line
US7067866B2 (en) * 2003-03-31 2006-06-27 Applied Spintronics Technology, Inc. MRAM architecture and a method and system for fabricating MRAM memories utilizing the architecture
US6785160B1 (en) * 2003-04-29 2004-08-31 Hewlett-Packard Development Company, L.P. Method of providing stability of a magnetic memory cell
US7078239B2 (en) 2003-09-05 2006-07-18 Micron Technology, Inc. Integrated circuit structure formed by damascene process
US6819586B1 (en) * 2003-10-24 2004-11-16 Hewlett-Packard Development Company, L.P. Thermally-assisted magnetic memory structures
US20050141148A1 (en) 2003-12-02 2005-06-30 Kabushiki Kaisha Toshiba Magnetic memory
US20050205952A1 (en) * 2004-03-19 2005-09-22 Jae-Hyun Park Magnetic random access memory cells having split sub-digit lines having cladding layers thereon and methods of fabricating the same
US6946698B1 (en) 2004-04-02 2005-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM device having low-k inter-metal dielectric
US20060039183A1 (en) * 2004-05-21 2006-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-sensing level MRAM structures
WO2005122259A1 (ja) * 2004-06-10 2005-12-22 Nec Corporation 磁気メモリ
US7221584B2 (en) * 2004-08-13 2007-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM cell having shared configuration
US20130082232A1 (en) 2011-09-30 2013-04-04 Unity Semiconductor Corporation Multi Layered Conductive Metal Oxide Structures And Methods For Facilitating Enhanced Performance Characteristics Of Two Terminal Memory Cells
US7407885B2 (en) * 2005-05-11 2008-08-05 Micron Technology, Inc. Methods of forming electrically conductive plugs
KR100682950B1 (ko) * 2005-07-28 2007-02-15 삼성전자주식회사 강유전체 기록매체 및 그 제조 방법
US7738287B2 (en) * 2007-03-27 2010-06-15 Grandis, Inc. Method and system for providing field biased magnetic memory devices
JP2009283843A (ja) * 2008-05-26 2009-12-03 Renesas Technology Corp 半導体装置及びその製造方法
US7833806B2 (en) 2009-01-30 2010-11-16 Everspin Technologies, Inc. Structure and method for fabricating cladded conductive lines in magnetic memories
KR101983137B1 (ko) * 2013-03-04 2019-05-28 삼성전기주식회사 파워 인덕터 및 그 제조방법
US10403424B2 (en) 2017-06-09 2019-09-03 Texas Instruments Incorporated Method to form magnetic core for integrated magnetic devices
CN112133820A (zh) * 2019-06-25 2020-12-25 中电海康集团有限公司 Mram底电极的制备方法

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Publication number Priority date Publication date Assignee Title
JP2728025B2 (ja) 1995-04-13 1998-03-18 日本電気株式会社 半導体装置の製造方法
ATE223108T1 (de) * 1995-04-24 2002-09-15 Infineon Technologies Ag Halbleiter-speichervorrichtung unter verwendung eines ferroelektrischen dielektrikums und verfahren zur herstellung
JPH09191084A (ja) * 1996-01-10 1997-07-22 Nec Corp 半導体装置及びその製造方法
US5732016A (en) * 1996-07-02 1998-03-24 Motorola Memory cell structure in a magnetic random access memory and a method for fabricating thereof
US6030877A (en) * 1997-10-06 2000-02-29 Industrial Technology Research Institute Electroless gold plating method for forming inductor structures
US5956267A (en) 1997-12-18 1999-09-21 Honeywell Inc Self-aligned wordline keeper and method of manufacture therefor
US6278165B1 (en) * 1998-06-29 2001-08-21 Kabushiki Kaisha Toshiba MIS transistor having a large driving current and method for producing the same
US5940319A (en) * 1998-08-31 1999-08-17 Motorola, Inc. Magnetic random access memory and fabricating method thereof
JP2000090658A (ja) * 1998-09-09 2000-03-31 Sanyo Electric Co Ltd 磁気メモリ素子
US6872993B1 (en) * 1999-05-25 2005-03-29 Micron Technology, Inc. Thin film memory device having local and external magnetic shielding
JP2001230468A (ja) * 2000-02-17 2001-08-24 Sharp Corp 磁気トンネル接合素子及びそれを用いた磁気メモリ
DE10106860A1 (de) * 2000-02-17 2001-08-30 Sharp Kk MTJ-Element und Magnetspeicher unter Verwendung eines solchen
US6211090B1 (en) * 2000-03-21 2001-04-03 Motorola, Inc. Method of fabricating flux concentrating layer for use with magnetoresistive random access memories
TW459374B (en) * 2000-08-30 2001-10-11 Mosel Vitelic Inc Method for forming magnetic layer of magnetic random access memory
US6555858B1 (en) * 2000-11-15 2003-04-29 Motorola, Inc. Self-aligned magnetic clad write line and its method of formation
US6413788B1 (en) * 2001-02-28 2002-07-02 Micron Technology, Inc. Keepers for MRAM electrodes

Also Published As

Publication number Publication date
JP2002334973A (ja) 2002-11-22
CN1374691A (zh) 2002-10-16
KR100855573B1 (ko) 2008-09-03
US20020127743A1 (en) 2002-09-12
EP1239489B1 (en) 2004-08-25
KR20030009078A (ko) 2003-01-29
EP1239489A1 (en) 2002-09-11
DE60201036T2 (de) 2005-08-11
DE60201036D1 (de) 2004-09-30
TW513803B (en) 2002-12-11
US6475812B2 (en) 2002-11-05

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