JP2002110865A - 回路装置 - Google Patents

回路装置

Info

Publication number
JP2002110865A
JP2002110865A JP2000295230A JP2000295230A JP2002110865A JP 2002110865 A JP2002110865 A JP 2002110865A JP 2000295230 A JP2000295230 A JP 2000295230A JP 2000295230 A JP2000295230 A JP 2000295230A JP 2002110865 A JP2002110865 A JP 2002110865A
Authority
JP
Japan
Prior art keywords
terminal
interposer
substrate
semiconductor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000295230A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002110865A5 (enExample
Inventor
Mie Matsuo
美恵 松尾
Nobuo Hayasaka
伸夫 早坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000295230A priority Critical patent/JP2002110865A/ja
Priority to US09/957,510 priority patent/US6614106B2/en
Priority to TW090123478A priority patent/TW538511B/zh
Publication of JP2002110865A publication Critical patent/JP2002110865A/ja
Publication of JP2002110865A5 publication Critical patent/JP2002110865A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2000295230A 2000-09-27 2000-09-27 回路装置 Pending JP2002110865A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000295230A JP2002110865A (ja) 2000-09-27 2000-09-27 回路装置
US09/957,510 US6614106B2 (en) 2000-09-27 2001-09-21 Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device
TW090123478A TW538511B (en) 2000-09-27 2001-09-24 Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000295230A JP2002110865A (ja) 2000-09-27 2000-09-27 回路装置

Publications (2)

Publication Number Publication Date
JP2002110865A true JP2002110865A (ja) 2002-04-12
JP2002110865A5 JP2002110865A5 (enExample) 2005-06-16

Family

ID=18777689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000295230A Pending JP2002110865A (ja) 2000-09-27 2000-09-27 回路装置

Country Status (3)

Country Link
US (1) US6614106B2 (enExample)
JP (1) JP2002110865A (enExample)
TW (1) TW538511B (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004282072A (ja) * 2003-03-14 2004-10-07 General Electric Co <Ge> インタポーザ、インタポーザパッケージ、及びそれらを使用したデバイス組立体
US6812557B2 (en) 2002-09-30 2004-11-02 Kabushiki Kaisha Toshiba Stacked type semiconductor device
US7095112B2 (en) 2002-09-19 2006-08-22 Kabushiki Kaisha Toshiba Semiconductor device, semiconductor package member, and semiconductor device manufacturing method
JP2007123520A (ja) * 2005-10-27 2007-05-17 Matsushita Electric Ind Co Ltd 積層型半導体モジュール
US8791544B2 (en) 2009-06-30 2014-07-29 Nec Corporation Semiconductor device, mounted substrate to be used in semiconductor device, and manufacturing method of mounted substrate

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525407B1 (en) * 2001-06-29 2003-02-25 Novellus Systems, Inc. Integrated circuit package
US20030150640A1 (en) * 2002-02-14 2003-08-14 Crippen Warren Stuart Silicon space transformer and method of manufacturing same
US20040084766A1 (en) * 2002-10-30 2004-05-06 Pei-Ying Shieh System-in-a-package device
JP2004327951A (ja) * 2003-03-06 2004-11-18 Shinko Electric Ind Co Ltd 半導体装置
US7566960B1 (en) * 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4377269B2 (ja) * 2004-03-19 2009-12-02 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4353861B2 (ja) 2004-06-30 2009-10-28 Ｎｅｃエレクトロニクス株式会社 半導体装置
EP2041789A2 (en) * 2006-06-20 2009-04-01 Nxp B.V. Power amplifier assembly
TWI326908B (en) * 2006-09-11 2010-07-01 Ind Tech Res Inst Packaging structure and fabricating method thereof
US20080192452A1 (en) * 2007-02-12 2008-08-14 Randall Michael S Passive electronic device
JP5450188B2 (ja) * 2010-03-16 2014-03-26 株式会社東芝 放射線検出装置、放射線検出装置の製造方法および画像撮影装置
US9082763B2 (en) * 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US9971970B1 (en) 2015-04-27 2018-05-15 Rigetti & Co, Inc. Microwave integrated quantum circuits with VIAS and methods for making the same
US11031341B2 (en) * 2017-03-29 2021-06-08 Intel Corporation Side mounted interconnect bridges
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) * 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5177594A (en) * 1991-01-09 1993-01-05 International Business Machines Corporation Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance
KR930001365A (ko) 1991-03-27 1993-01-16 빈센트 죠셉 로너 복합 플립 칩 반도체 소자와 그 제조 및 번-인(burning-in) 방법
JPH10150141A (ja) 1996-11-15 1998-06-02 Sony Corp 半導体装置及びこの半導体装置の実装方法
JP3604248B2 (ja) * 1997-02-25 2004-12-22 沖電気工業株式会社 半導体装置の製造方法
JP3914615B2 (ja) 1997-08-19 2007-05-16 住友電気工業株式会社 半導体発光素子及びその製造方法
US6281042B1 (en) * 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6137167A (en) * 1998-11-24 2000-10-24 Micron Technology, Inc. Multichip module with built in repeaters and method
JP2000183081A (ja) * 1998-12-16 2000-06-30 Matsushita Electronics Industry Corp 半導体装置の製造方法および製造装置
JP2000323701A (ja) 1999-05-10 2000-11-24 Citizen Watch Co Ltd 半導体装置およびその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095112B2 (en) 2002-09-19 2006-08-22 Kabushiki Kaisha Toshiba Semiconductor device, semiconductor package member, and semiconductor device manufacturing method
US6812557B2 (en) 2002-09-30 2004-11-02 Kabushiki Kaisha Toshiba Stacked type semiconductor device
JP2004282072A (ja) * 2003-03-14 2004-10-07 General Electric Co <Ge> インタポーザ、インタポーザパッケージ、及びそれらを使用したデバイス組立体
JP2007123520A (ja) * 2005-10-27 2007-05-17 Matsushita Electric Ind Co Ltd 積層型半導体モジュール
US8008766B2 (en) 2005-10-27 2011-08-30 Panasonic Corporation Stacked semiconductor module
US8159061B2 (en) 2005-10-27 2012-04-17 Panasonic Corporation Stacked semiconductor module
US8791544B2 (en) 2009-06-30 2014-07-29 Nec Corporation Semiconductor device, mounted substrate to be used in semiconductor device, and manufacturing method of mounted substrate

Also Published As

Publication number Publication date
TW538511B (en) 2003-06-21
US6614106B2 (en) 2003-09-02
US20020036340A1 (en) 2002-03-28

Similar Documents

Publication Publication Date Title
JP2002110865A (ja) 回路装置
US7317622B2 (en) Method and apparatus for supplying power to a semiconductor device using a capacitor DC shunt
US20060060962A1 (en) Electronic package having a folded package substrate
TWI248623B (en) Array capacitors with voids to enable a full-grid socket
EP1143515A3 (en) Wiring substrate, method of manufacturing the same and semiconductor device
US6884087B2 (en) Socket with multiple contact pad area socket contacts
JP2002057418A (ja) プリント配線基板
US7952442B2 (en) Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure
JP2001053185A (ja) 半導体パッケージ
JPH06181375A (ja) 実装補助部品及びこれを用いた半導体装置
JPH0538907U (ja) 集積回路パツケージ
JP2000260661A (ja) チップ部品およびチップ部品実装基板
JP2003068859A (ja) 半導体チップ及びこれを用いた半導体装置
JPH05211279A (ja) 混成集積回路
JPH11340589A (ja) 可撓性回路基板
JPH019160Y2 (enExample)
JP2000124353A (ja) 配線基板及びこれを用いた半導体装置並びに電子装置
JPH03109342U (enExample)
JPH1041429A (ja) 電子デバイス
JPH0492461A (ja) 混成集積回路
JP2000223618A (ja) 半導体装置
JPH08181241A (ja) チップキャリア及びこのチップキャリアを用いた半導体装置
JPH11284113A (ja) 半導体集積デバイスの放熱機構
JPS59161057A (ja) 半導体集積回路
JPS6313371A (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040917

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040917

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070724

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070921

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20071030