JP2004282072A - インタポーザ、インタポーザパッケージ、及びそれらを使用したデバイス組立体 - Google Patents
インタポーザ、インタポーザパッケージ、及びそれらを使用したデバイス組立体 Download PDFInfo
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Abstract
【解決手段】 インタポーザは、半導体物質の基板と、該基板の第1のメイン表面上の第1の入力/出力接点(122、340、360)と第1の入力/出力接点に電気的に接続(124、320)される第2のメイン表面上の第2の入力/出力接点(126、330、415)とを有する。第1の入出力接点は、それに対してインタポーザを取り付けるデバイス(140、210、310、410)の入出力パッド(142)に取り付けるためのものである。第2の入出力接点は、それに対してもインタポーザを取り付ける構成要素(220)に対する結合を可能にする。
【選択図】 図1
Description
110 インタポーザパッケージ
120 インタポーザ
122 第1の入力/出力接点
124 ビア
126 第2の入力/出力接点
130 カプセル
132 差込み可能接点
140 デバイス
142 入力/出力パッド
150 ハンダ付け
Claims (10)
- 半導体物質で形成された基板を含み、前記基板の第1のメイン表面上に置かれた第1の入力/出力接点(122、340、360)と該基板の第2のメイン表面上に置かれた第2の入力/出力接点(126、330、415)とを有するインタポーザ(120、200、300、400)を含み、
前記第2の入力/出力接点が、前記第1の入力/出力接点に電気的に接続(124、320)されており、
前記基板の第1のメイン表面上に置かれた前記第1の入力/出力接点(122、340、360)が、それに対して前記インタポーザ(120、200、300、400)を取り付けようとしているデバイス(140、210、310、410)の入力/出力パッド(142)に取り付けるためのものであり、
前記第2のメイン表面上に置かれた前記第2の入力/出力接点(126、330、415)が、それに対しても前記インタポーザを取り付けようとしている構成要素(220)の接点に対する結合を可能にする、
ことを特徴とする構造体。 - 前記インタポーザ基板の第1のメイン表面上に置かれた前記第1の入力/出力接点(122、340、360)が、それに対して前記インタポーザを取り付けようとしている前記デバイス(140、210、310、410)の入力/出力パッド(142)と対応する形状サイズを有することを特徴とする、請求項1に記載の構造体。
- 前記デバイス(140、210、310、410)が、x、y表面区域を有する集積回路ベアチップを含み、前記インタポーザ(120、200、300、400)が、前記集積回路ベアチップのx、y表面区域と同じサイズにされた表面区域を有することを特徴とする、請求項1に記載の構造体。
- 前記集積回路ベアチップ(140、210、310、410)が、第1の集積回路チップを含み、前記構成要素(220)が、第2の集積回路チップを含み、前記インタポーザ(120、200、300、400)が、前記第1の集積回路チップと前記第2の集積回路チップとの間の電気的接続を可能にすることを特徴とする、請求項3に記載の構造体。
- 前記半導体物質が、シリコン、炭化ケイ素、及びガリウム砒素の少なくとも1つを含むことを特徴とする、請求項1に記載の構造体。
- 前記デバイスが、半導体物質で形成された基板を有し、
前記インタポーザ基板の半導体物質が、前記デバイス基板の半導体物質と少なくとも部分的に一致していることを特徴とする、請求項1に記載の構造体。 - 前記第1のメイン表面上に置かれた前記第1の入力/出力接点(122、340、360)が、前記インタポーザ基板の第2のメイン表面上に置かれた前記第2の入力/出力接点(126、330、415)とは異なるピッチを有することを特徴とする、請求項1に記載の構造体。
- 前記インタポーザ(120)が、インタポーザパッケージ(110)を更に含み、前記インタポーザパッケージが、前記インタポーザ基板の第2のメイン表面上に置かれた前記第2の入力/出力接点(126)の少なくとも一部分を囲むカプセル(130)を有することを特徴とする、請求項1に記載の構造体。
- その表面上に置かれた入力/出力パッド(142)を有する集積回路デバイス(140、210、310、410)と、
半導体物質で形成された基板を有し、前記基板の第1のメイン表面上に置かれた第1の入力/出力接点(122、340、360)と該基板の第2のメイン表面上に置かれかつ前記第1の入力/出力接点に電気的に接続(124、320)された第2の入力/出力接点(126、330、415)とを有するインタポーザ(120、200、300、400)と、を含み、
前記基板の第1のメイン表面上に置かれた前記第1の入力/出力接点(122、340、360)が、前記集積回路デバイス(140、210、310、410)の入力/出力パッド(142)に電気的に取り付けられ、前記第2のメイン表面上に置かれた前記第2の入力/出力接点(126、330、415)が、それに対しても前記インタポーザを取り付けることができる構成要素(220)の接点に対する結合を可能にする、
ことを特徴とする構造体(100)。 - デバイス(140、210、310、410)の入力/出力パッド(142)に接触させるための方法であって、
半導体物質で形成された基板を有し、前記基板の第1のメイン表面上に置かれた第1の入力/出力接点(122、340、360)と該基板の第2のメイン表面上に置かれかつそれに対して前記第1の入力/出力接点が電気的に接続(124、320)された第2の入力/出力接点(126、330、415)とを含むインタポーザ(120、200、300、400)を準備する段階と、
前記インタポーザ(120、200、300、400)の第1の入力/出力接点(122、340、360)をデバイス(140、210、310、410)の入力/出力パッド(142)に電気的に接続することにより、該インタポーザ(120、200、300、400)を該デバイスに対して電気的に接続する段階と、
を含むことを特徴とする方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/388,997 | 2003-03-14 | ||
US10/388,997 US6819001B2 (en) | 2003-03-14 | 2003-03-14 | Interposer, interposer package and device assembly employing the same |
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JP2004282072A true JP2004282072A (ja) | 2004-10-07 |
JP2004282072A5 JP2004282072A5 (ja) | 2007-04-19 |
JP5568205B2 JP5568205B2 (ja) | 2014-08-06 |
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JP2004070540A Expired - Lifetime JP5568205B2 (ja) | 2003-03-14 | 2004-03-12 | インタポーザ、インタポーザパッケージ、及びそれらを使用したデバイス組立体 |
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US (1) | US6819001B2 (ja) |
JP (1) | JP5568205B2 (ja) |
CN (1) | CN100454532C (ja) |
DE (1) | DE102004012595A1 (ja) |
IL (1) | IL160581A0 (ja) |
NL (1) | NL1025639C2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008526343A (ja) * | 2005-01-11 | 2008-07-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | マイクロビームフォーマ及び医用超音波システム用再配布相互接続 |
JP2008545501A (ja) * | 2005-06-07 | 2008-12-18 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 超音波センサ組立体に対するバッキングブロック |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6990176B2 (en) | 2003-10-30 | 2006-01-24 | General Electric Company | Methods and apparatus for tileable sensor array |
US7019346B2 (en) * | 2003-12-23 | 2006-03-28 | Intel Corporation | Capacitor having an anodic metal oxide substrate |
US7242073B2 (en) * | 2003-12-23 | 2007-07-10 | Intel Corporation | Capacitor having an anodic metal oxide substrate |
US20060091538A1 (en) * | 2004-11-04 | 2006-05-04 | Kabadi Ashok N | Low profile and tight pad-pitch land-grid-array (LGA) socket |
US7230334B2 (en) * | 2004-11-12 | 2007-06-12 | International Business Machines Corporation | Semiconductor integrated circuit chip packages having integrated microchannel cooling modules |
KR100652397B1 (ko) * | 2005-01-17 | 2006-12-01 | 삼성전자주식회사 | 매개 인쇄회로기판을 사용하는 적층형 반도체 패키지 |
JP4507101B2 (ja) * | 2005-06-30 | 2010-07-21 | エルピーダメモリ株式会社 | 半導体記憶装置及びその製造方法 |
JP2007139912A (ja) * | 2005-11-15 | 2007-06-07 | Sharp Corp | 駆動素子実装表示装置 |
JP4744360B2 (ja) * | 2006-05-22 | 2011-08-10 | 富士通株式会社 | 半導体装置 |
TWI326908B (en) * | 2006-09-11 | 2010-07-01 | Ind Tech Res Inst | Packaging structure and fabricating method thereof |
US20080068815A1 (en) * | 2006-09-18 | 2008-03-20 | Oliver Richard Astley | Interface Assembly And Method for Integrating A Data Acquisition System on a Sensor Array |
US7518226B2 (en) * | 2007-02-06 | 2009-04-14 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
KR101387701B1 (ko) * | 2007-08-01 | 2014-04-23 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조방법 |
KR101623880B1 (ko) * | 2008-09-24 | 2016-05-25 | 삼성전자주식회사 | 반도체 패키지 |
US7973272B2 (en) * | 2009-03-09 | 2011-07-05 | Bae Systems Information And Electronic Systems Integration, Inc. | Interface techniques for coupling a microchannel plate to a readout circuit |
US7923290B2 (en) * | 2009-03-27 | 2011-04-12 | Stats Chippac Ltd. | Integrated circuit packaging system having dual sided connection and method of manufacture thereof |
US7936060B2 (en) * | 2009-04-29 | 2011-05-03 | International Business Machines Corporation | Reworkable electronic device assembly and method |
US20110180317A1 (en) * | 2009-09-11 | 2011-07-28 | Eiji Takahashi | Electronic component package, method for producing the same and interposer |
US8008121B2 (en) * | 2009-11-04 | 2011-08-30 | Stats Chippac, Ltd. | Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate |
US8405229B2 (en) * | 2009-11-30 | 2013-03-26 | Endicott Interconnect Technologies, Inc. | Electronic package including high density interposer and circuitized substrate assembly utilizing same |
US8363418B2 (en) * | 2011-04-18 | 2013-01-29 | Morgan/Weiss Technologies Inc. | Above motherboard interposer with peripheral circuits |
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US9006908B2 (en) * | 2012-08-01 | 2015-04-14 | Marvell Israel (M.I.S.L) Ltd. | Integrated circuit interposer and method of manufacturing the same |
WO2014121300A2 (en) * | 2013-02-04 | 2014-08-07 | American Semiconductor, Inc. | Photonic data transfer assembly |
US20140264938A1 (en) * | 2013-03-14 | 2014-09-18 | Douglas R. Hackler, Sr. | Flexible Interconnect |
JP6260806B2 (ja) * | 2013-09-27 | 2018-01-17 | インテル・コーポレーション | 両面ダイパッケージ |
JP2015082524A (ja) * | 2013-10-21 | 2015-04-27 | ソニー株式会社 | 配線基板、半導体装置 |
US9613857B2 (en) * | 2014-10-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection structure and method |
US11309192B2 (en) | 2018-06-05 | 2022-04-19 | Intel Corporation | Integrated circuit package supports |
DE102020206769B3 (de) * | 2020-05-29 | 2021-06-10 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein | Mikroelektronische anordnung und verfahren zur herstellung derselben |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0233960A (ja) * | 1988-07-23 | 1990-02-05 | Nec Corp | 半導体装置 |
JPH04159740A (ja) | 1990-10-23 | 1992-06-02 | Matsushita Electric Ind Co Ltd | チップのボンディング方法 |
JPH05198697A (ja) * | 1992-01-20 | 1993-08-06 | Fujitsu Ltd | シリコン基板金属ビア形成方法およびマルチチップモジュール製造方法 |
JPH06169031A (ja) * | 1993-08-30 | 1994-06-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH08508613A (ja) * | 1993-03-29 | 1996-09-10 | ゼネラル・データコム・インコーポレーテッド | ばね偏倚式テーパー付き接点要素 |
JPH08236658A (ja) * | 1995-02-27 | 1996-09-13 | Nec Eng Ltd | 集積回路パッケージ |
JP2000299422A (ja) * | 1999-03-18 | 2000-10-24 | Internatl Business Mach Corp <Ibm> | 電気的接続を提供する導電性装置、集積回路パッケージ/アセンブリおよび取り付け方法 |
JP2000307025A (ja) | 1999-04-23 | 2000-11-02 | Matsushita Electric Ind Co Ltd | 電子部品とその製造方法および電子部品実装体 |
JP2001217388A (ja) * | 2000-02-01 | 2001-08-10 | Sony Corp | 電子装置およびその製造方法 |
JP2002083846A (ja) | 2000-09-07 | 2002-03-22 | Nec Corp | 実装用ピン及び実装装置 |
JP2002110865A (ja) * | 2000-09-27 | 2002-04-12 | Toshiba Corp | 回路装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3982268A (en) * | 1973-10-30 | 1976-09-21 | General Electric Company | Deep diode lead throughs |
US5258648A (en) * | 1991-06-27 | 1993-11-02 | Motorola, Inc. | Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery |
JP3863213B2 (ja) * | 1996-03-27 | 2006-12-27 | 株式会社ルネサステクノロジ | 半導体装置 |
US6219237B1 (en) * | 1998-08-31 | 2001-04-17 | Micron Technology, Inc. | Structure and method for an electronic assembly |
JP2000138313A (ja) * | 1998-10-30 | 2000-05-16 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6459582B1 (en) * | 2000-07-19 | 2002-10-01 | Fujitsu Limited | Heatsink apparatus for de-coupling clamping forces on an integrated circuit package |
US7271491B1 (en) * | 2000-08-31 | 2007-09-18 | Micron Technology, Inc. | Carrier for wafer-scale package and wafer-scale package including the carrier |
DE10142116A1 (de) * | 2001-08-30 | 2002-11-14 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zu seiner Herstellung |
CN2534677Y (zh) * | 2002-01-21 | 2003-02-05 | 威盛电子股份有限公司 | 可插拔集成电路装置 |
-
2003
- 2003-03-14 US US10/388,997 patent/US6819001B2/en not_active Expired - Lifetime
-
2004
- 2004-02-26 IL IL16058104A patent/IL160581A0/xx unknown
- 2004-03-04 NL NL1025639A patent/NL1025639C2/nl not_active IP Right Cessation
- 2004-03-09 CN CNB2004100282983A patent/CN100454532C/zh not_active Expired - Lifetime
- 2004-03-12 DE DE102004012595A patent/DE102004012595A1/de not_active Withdrawn
- 2004-03-12 JP JP2004070540A patent/JP5568205B2/ja not_active Expired - Lifetime
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0233960A (ja) * | 1988-07-23 | 1990-02-05 | Nec Corp | 半導体装置 |
JPH04159740A (ja) | 1990-10-23 | 1992-06-02 | Matsushita Electric Ind Co Ltd | チップのボンディング方法 |
JPH05198697A (ja) * | 1992-01-20 | 1993-08-06 | Fujitsu Ltd | シリコン基板金属ビア形成方法およびマルチチップモジュール製造方法 |
JPH08508613A (ja) * | 1993-03-29 | 1996-09-10 | ゼネラル・データコム・インコーポレーテッド | ばね偏倚式テーパー付き接点要素 |
JPH06169031A (ja) * | 1993-08-30 | 1994-06-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH08236658A (ja) * | 1995-02-27 | 1996-09-13 | Nec Eng Ltd | 集積回路パッケージ |
JP2000299422A (ja) * | 1999-03-18 | 2000-10-24 | Internatl Business Mach Corp <Ibm> | 電気的接続を提供する導電性装置、集積回路パッケージ/アセンブリおよび取り付け方法 |
JP2000307025A (ja) | 1999-04-23 | 2000-11-02 | Matsushita Electric Ind Co Ltd | 電子部品とその製造方法および電子部品実装体 |
JP2001217388A (ja) * | 2000-02-01 | 2001-08-10 | Sony Corp | 電子装置およびその製造方法 |
JP2002083846A (ja) | 2000-09-07 | 2002-03-22 | Nec Corp | 実装用ピン及び実装装置 |
JP2002110865A (ja) * | 2000-09-27 | 2002-04-12 | Toshiba Corp | 回路装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008526343A (ja) * | 2005-01-11 | 2008-07-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | マイクロビームフォーマ及び医用超音波システム用再配布相互接続 |
JP2008545501A (ja) * | 2005-06-07 | 2008-12-18 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 超音波センサ組立体に対するバッキングブロック |
Also Published As
Publication number | Publication date |
---|---|
US6819001B2 (en) | 2004-11-16 |
DE102004012595A1 (de) | 2004-10-28 |
NL1025639A1 (nl) | 2004-09-16 |
US20040178484A1 (en) | 2004-09-16 |
JP5568205B2 (ja) | 2014-08-06 |
CN100454532C (zh) | 2009-01-21 |
NL1025639C2 (nl) | 2005-05-26 |
IL160581A0 (en) | 2004-07-25 |
CN1531081A (zh) | 2004-09-22 |
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