TW538511B - Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device - Google Patents

Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device Download PDF

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Publication number
TW538511B
TW538511B TW090123478A TW90123478A TW538511B TW 538511 B TW538511 B TW 538511B TW 090123478 A TW090123478 A TW 090123478A TW 90123478 A TW90123478 A TW 90123478A TW 538511 B TW538511 B TW 538511B
Authority
TW
Taiwan
Prior art keywords
terminal
circuit
patent application
aforementioned
interposer
Prior art date
Application number
TW090123478A
Other languages
English (en)
Chinese (zh)
Inventor
Mie Matsuo
Nobuo Hayasaka
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW538511B publication Critical patent/TW538511B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
TW090123478A 2000-09-27 2001-09-24 Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device TW538511B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000295230A JP2002110865A (ja) 2000-09-27 2000-09-27 回路装置

Publications (1)

Publication Number Publication Date
TW538511B true TW538511B (en) 2003-06-21

Family

ID=18777689

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090123478A TW538511B (en) 2000-09-27 2001-09-24 Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device

Country Status (3)

Country Link
US (1) US6614106B2 (enExample)
JP (1) JP2002110865A (enExample)
TW (1) TW538511B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525407B1 (en) * 2001-06-29 2003-02-25 Novellus Systems, Inc. Integrated circuit package
US20030150640A1 (en) * 2002-02-14 2003-08-14 Crippen Warren Stuart Silicon space transformer and method of manufacturing same
JP2004111676A (ja) 2002-09-19 2004-04-08 Toshiba Corp 半導体装置、半導体パッケージ用部材、半導体装置の製造方法
JP3828473B2 (ja) 2002-09-30 2006-10-04 株式会社東芝 積層型半導体装置及びその製造方法
US20040084766A1 (en) * 2002-10-30 2004-05-06 Pei-Ying Shieh System-in-a-package device
JP2004327951A (ja) * 2003-03-06 2004-11-18 Shinko Electric Ind Co Ltd 半導体装置
US6819001B2 (en) * 2003-03-14 2004-11-16 General Electric Company Interposer, interposer package and device assembly employing the same
US7566960B1 (en) 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
JP4377269B2 (ja) * 2004-03-19 2009-12-02 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4353861B2 (ja) 2004-06-30 2009-10-28 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4512545B2 (ja) 2005-10-27 2010-07-28 パナソニック株式会社 積層型半導体モジュール
WO2008007258A2 (en) * 2006-06-20 2008-01-17 Nxp B.V. Power amplifier assembly
TWI326908B (en) * 2006-09-11 2010-07-01 Ind Tech Res Inst Packaging structure and fabricating method thereof
US20080192452A1 (en) * 2007-02-12 2008-08-14 Randall Michael S Passive electronic device
WO2011001992A1 (ja) 2009-06-30 2011-01-06 日本電気株式会社 半導体装置、該装置に用いられる実装基板及び該実装基板の製造方法
JP5450188B2 (ja) * 2010-03-16 2014-03-26 株式会社東芝 放射線検出装置、放射線検出装置の製造方法および画像撮影装置
US9082763B2 (en) * 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US10068181B1 (en) 2015-04-27 2018-09-04 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafer and methods for making the same
WO2018182598A1 (en) * 2017-03-29 2018-10-04 Intel Corporation Side mounted interconnect bridges
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) * 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5177594A (en) * 1991-01-09 1993-01-05 International Business Machines Corporation Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance
JPH05211202A (ja) 1991-06-27 1993-08-20 Motorola Inc 複合フリップ・チップ半導体装置とその製造およびバーンインの方法
JPH10150141A (ja) 1996-11-15 1998-06-02 Sony Corp 半導体装置及びこの半導体装置の実装方法
JP3604248B2 (ja) * 1997-02-25 2004-12-22 沖電気工業株式会社 半導体装置の製造方法
JP3914615B2 (ja) 1997-08-19 2007-05-16 住友電気工業株式会社 半導体発光素子及びその製造方法
US6281042B1 (en) * 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6137167A (en) * 1998-11-24 2000-10-24 Micron Technology, Inc. Multichip module with built in repeaters and method
JP2000183081A (ja) * 1998-12-16 2000-06-30 Matsushita Electronics Industry Corp 半導体装置の製造方法および製造装置
JP2000323701A (ja) 1999-05-10 2000-11-24 Citizen Watch Co Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US20020036340A1 (en) 2002-03-28
US6614106B2 (en) 2003-09-02
JP2002110865A (ja) 2002-04-12

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