CN107452694B - 嵌入式封装结构 - Google Patents
嵌入式封装结构 Download PDFInfo
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Abstract
本公开提供一种嵌入式封装结构,包含绝缘基板、第一导电层、第二导电层、电子元件及无源元件。绝缘基板具有第一导电通孔及第二导电通孔。第一导电层设置于绝缘基板的顶面且与第一导电通孔连接导通。第二导电层设置于绝缘层的底面且与第二导电通孔连接导通。电子元件内埋于绝缘基板内,且电子元件的多个第一导接端是通过第一导电通孔及第二导电通孔而与第一导电层及第二导电层相导通。无源元件是隔离地设置于电子元件的第一侧边,且至少部分嵌设于绝缘基板。本公开提供的嵌入式封装结构可以使嵌入式封装结构的整体厚度薄化,从而使嵌入式封装结构得以应用于超薄电子产品。
Description
技术领域
本公开涉及电气元件组件的制造技术领域,具体而言,涉及一种嵌入式封装结构。
背景技术
近年来随着便携式电子产品的蓬勃发展,各类相关产品逐渐朝向高密度、高性能以及轻、薄、短、小的趋势发展。再者,许多电子产品的内部电路已朝模块化发展,借此使许多功能整合在一电路模块中。以常见的电路模块例如电源模块(power module)为例,其包括例如直流-直流转换器(DC to DC converter)、直流-交流转换器(DC to AC converter)或交流-直流转换器(AC to DC converter)等等,且通常将例如集成电路、电容器、电阻器、电感、变压器、二极管、晶体管等电子元件整合为电源模块,进而可将电源模块安装于主机板或系统电路板上。
目前,嵌入式封装结构已广泛地被使用,且其构造及制造程序简述如下。首先,将具有导接端的电子元件(例如主动元件)内埋于绝缘基板中,并利用激光钻孔方式在绝缘基板中形成至少一通孔,且将导电物质填充于通孔中以形成导电通孔,的后布上导电层使其与导电通孔接触,再将无源元件安装于前述结构上,藉此使无源元件可与电子元件电性连接。由于无源元件与电子元件是通过导电层与导电通孔的导通路径电性连接且彼此垂直堆迭设置,如此可节省主机板或系统电路板的使用面积。
然而,由于无源元件、电子元件及导电层垂直堆迭设置,因此会造成嵌入式封装结构的整体厚度较厚,例如大于1000μm,如此一来,对于某些超薄电子产品(例如智能手机、平板电脑),传统的嵌入式封装结构将无法符合实际应用需求。
发明内容
本公开的目的为提供一种嵌入式封装结构,其是将电子元件与无源元件相隔离地嵌设于绝缘基板中,以使无源元件与电子元件水平设置而实现封装,藉此使嵌入式封装结构的整体厚度可以薄化,从而使嵌入式封装结构得以应用于超薄电子产品。
本公开的另一目的为提供一种嵌入式封装结构,其封装结构较为扁平薄化且易于制造,且具较高功率密度、优选电气特性与热管理效能。
根据本公开的构想,本公开提供一种嵌入式封装结构,包含绝缘基板、第一导电层、第二导电层、电子元件、第一绝缘材料、第二绝缘材料及无源元件。绝缘基板具有至少一第一导电通孔及至少一第二导电通孔。第一导电层设置于绝缘基板的顶面上,且与至少一第一导电通孔连接导通。第二导电层设置于绝缘层的底面上,且与至少一第二导电通孔连接导通。电子元件内埋于绝缘基板内,且具有多个第一导接端,其中多个第一导接端是通过至少一第一导电通孔及至少一第二导电通孔而与第一导电层及第二导电层相导通。第一绝缘材料覆盖于第一导电层的外侧面,且部分覆盖于绝缘基板的顶面。第二绝缘材料覆盖于第二导电层的外侧面,且部分覆盖于绝缘基板的底面。无源元件隔离地设置于电子元件的第一侧边,且至少部分嵌设于绝缘基板。
根据本公开的另一构想,本公开提供一种嵌入式封装结构,该嵌入式封装结构包含介电基板、电子元件、至少一第一重布线层、无源元件及第二重布线层。介电基板具有第一区域以及第二区域,其中第二区域邻近于第一区域。电子元件是嵌设于介电基板的第一区域。该至少一第一重布线层是形成于介电基板的第一区域,且与电子元件电连接。无源元件是嵌设于介电基板,且至少部分设置于介电基板的第二区域。第二重布线层设置于介电基板的一表面,且第二重布线层是位于第一区域与第二区域,并且与无源元件及电子元件电连接。无源元件的厚度大于电子元件的厚度。
附图说明
图1为本公开第一优选实施例的嵌入式封装结构的结构示意图。
图2A至图2E为图1所示的嵌入式封装结构的制作流程示意图。
图3为本公开第二优选实施例的嵌入式封装结构的结构的示意图。
图4为本公开第三优选实施例的嵌入式封装结构的结构示意图。
图5为本公开第四优选实施例的嵌入式封装结构的结构示意图。
具体实施方式
体现本公开特征与优点的一些典型实施例将在后段的说明中详细叙述。应理解的是本公开能够在不同的实施方式上具有各种的变化,其皆不脱离本公开的范围,且其中的说明及附图在本质上是当作对其进行说明用,而非架构于限制本公开。
图1为本公开第一优选实施例的嵌入式封装结构的结构示意图,以及图2A至图2E为图1所示的嵌入式封装结构的制作流程示意图。如图1及图2A至图2E所示,本公开的嵌入式封装结构1包含绝缘基板10、电子元件11、第一导电层12、第二导电层13、第一绝缘材料14a、第二绝缘材料14b及无源元件15。其中,电子元件11内埋于绝缘基板10内,且具有多个第一导接端110。绝缘基板10具有多个导电通孔(via)103及多个导电通孔104。第一导电层12设置于绝缘基板10的顶面101上,且暴露部分的绝缘基板10的顶面101。再者,第一导电层12与导电通孔103连接而导通。第二导电层13设置于绝缘基板10的底面102上,且通过第二导电层13而暴露部分的绝缘基板10的底面102。再者,第二导电层13与导电通孔104连接而导通。位于电子元件11的上表面111的第一导接端110与导电通孔103连接而导通,且位于电子元件11的下表面112的第一导接端110与导电通孔104连接而导通。因此,通过多个第一导接端110、导电通孔103及导电通孔104,电子元件11与第一导电层12及第二导电层13连接而导通。第一绝缘材料14a是覆盖于第一导电层12的外侧面12a,且部分覆盖于绝缘基板10的顶面101。第二绝缘材料14b是覆盖于第二导电层13的外侧面13a,且部分覆盖于绝缘基板10的底面102。无源元件15是隔离地设置于电子元件11的第一侧边而与电子元件11相互水平设置,且至少部分埋设于绝缘基板10。此外,无源元件15具有一个或多个第二导接端150。
于本实施例中,嵌入式封装结构1具有开槽15a设置于电子元件11的侧边,该开槽15a是贯穿第一绝缘材料14a、第二绝缘材料14b及绝缘基板10,其中无源元件15是至少部分地设置于开槽15a中,以通过第一绝缘材料14a、第二绝缘材料14b及绝缘基板10而与电子元件11相隔离。于一些实施例中,开槽15a可利用例如但不限于激光穿孔的方式穿透位于电子元件11的侧边的第一绝缘材料14a、绝缘基板10及第二绝缘材料14b而形成。再者,开槽15a大于无源元件15。因此,当无源元件15置入开槽15a内时,无源元件15与开槽15a的内壁之间具有空隙,且无源元件15可至少部分地嵌设于绝缘基板10、第一绝缘材料14a及第二绝缘材料14b。
于本实施例中,嵌入式封装结构1还包含固着材料16、第三导电层17、第四导电层18、多个导电侧边10c及穿槽19。其中,第三导电层17设置于第一绝缘材料14a的顶面141上,且通过第三导电层17而暴露部分的第一绝缘材料14a的顶面141。
固着材料16是部分覆盖于第一绝缘材料14a的顶面141、第三导电层17的外侧面17a及无源元件15的外侧面155,使第一绝缘材料14a、第三导电层17及无源元件15之间通过固着材料16而相互粘着固设,且固着材料16是填设于无源元件15与开槽15a内壁之间的空隙,从而使无源元件15稳固地设置于开槽15a中。于此实施例中,固着材料16还包含多个导电通道106,导电通道106与第三导电层17的顶面17a连接,且多个导电通道106与无源元件15的对应的第二导接端150连接而导通。另外,第四导电层18设置于固着材料16的顶面161,且与多个导电通道106的顶面相连接,且通过第四导电层18而暴露部分的固着材料16的顶面161。
于本实施例中,第一绝缘材料14a还包含多个导电通孔105,多个导电通孔105的第一端是与第一导电层12的外侧面12a相连接,多个导电通孔105的第二端是与第三导电层17的底面相连接,且通过多个导电通孔103而与电子元件11的上表面111对应的第一导接端110连接而导通。
穿槽19是位于无源元件15与电子元件11之间,且可利用例如但不限于激光穿孔的方式形成。穿槽19包含第一内侧壁10a以及相对于第一内侧壁10a的第二内侧壁10b。嵌入式封装结构1还包括第三绝缘材料14c,其是设置于穿槽19内且与第一绝缘材料14a及第二绝缘材料14b相连接。此外,多个导电侧边10c是分别覆盖于第一内侧壁10a及第二内侧壁10b上,且与第一导电层12及第二导电层13相连接而导通。通过穿槽19的设置,可使电子元件11与无源元件15之间的绝缘效果强化。
于一些实施例中,第一导电层12、第二导电层13、第三导电层17及第四导电层18可分别以例如但不限于蚀刻方式而形成一个或是多个彼此独立且隔离的第一导电图形、第二导电图形、第三导电图形及第四导电图形。如图1所示,第一导电层12的第一导电图形会与对应的导电通孔103及导电通孔105连接而导通,第二导电层13的第二导电图形会与对应的导电通孔104连接而导通,第三导电层17的第三导电图形会与对应的导电通孔105及导电通道106连接而导通,第四导电层18的第四导电图形会与对应的导电通道106连接而导通。第一导电层12、第二导电层13、第三导电层17以及第四导电层18可分别由例如但不限于铜或任何其他适当的导电材料所构成,且分别以例如但不限于电镀或沉积方式形成。此外,导电通孔103位于绝缘基板10中,并暴露于绝缘基板10的顶面101且与第一导电层12连接而导通。导电通孔104同样位于绝缘基板10中,并暴露于绝缘基板10的底面102且与第二导电层13连接而导通。多个导电通孔103及多个导电通孔104的形成方式可先以例如但不限于激光钻孔、机械钻孔或是微影(Photolithography)蚀刻成孔方式于绝缘基板10中形成多个孔洞,之后再于该多个孔洞中以例如但不限于填充或电镀方式将导电物质形成于该多个孔洞中,以形成多个导电通孔103及多个导电通孔104。另外,导电通孔105位于第一绝缘材料14a中,并暴露于第一绝缘材料14a的顶面141且与第三导电层17连接而导通。导电通孔105的形成方式与前述导电通孔103及导电通孔104相同,故不再此赘述。
于一些实施例中,绝缘基板10的材料可为但不限于是预浸(prepreg)材料或是其他具高热传导系数的绝缘材料,而第一绝缘材料14a、第二绝缘材料14b及第三绝缘材料14c可为但不限于是由防焊油墨(Solder Mask)所构成,而固着材料16可为但不限于是由一或多绝缘材料例如防焊油墨(Solder Mask)所构成。
于本实施例中,电子元件11可为主动元件,例如但不限于集成电路芯片、整合性功率元件、金属氧化物半导体场效晶体管(MOSFET)、绝缘闸双极性晶体管(Insulated-gatebipolar transistor,IGBT)等,且电子元件11位于多个导电通孔103以及多个导电通孔104之间。位于电子元件11的上表面111的第一导接端110是通过导电通孔103而与对应的第一导电层12的第一导电图形连接而导通。位于电子元件11的下表面112的第一导接端110是通过导电通孔104与对应的第二导电层13的第二导电图形连接而导通。此外,无源元件15可为但不限于电容、电阻、电感等。于一实施例中,无源元件15包括扼流器(choke)。无源元件15的第二导接端150是通过导电通道106而与对应的第四导电层18的第四导电图形连接而导通。
于本实施例中,导电通孔105与第三导电层17是架构为一重布线层(Re-distribution layer,RDL),且导电通道106与第四导电层18是架构为另一重布线层(RDL),且第四导电层18可架构为与一系统电路板导接的接触垫。
根据本公开的构想,嵌入式封装结构1包括介电基板、电子元件11、至少一第一重布线层、无源元件15及第二重布线层。介电基板具有第一区域以及第二区域,其中第二区域邻近于第一区域。介电基板包括绝缘基板10、第一绝缘材料14a、第二绝缘材料14b及固着材料16。电子元件11嵌设于介电基板的第一区域。该至少一第一重布线层是形成于介电基板的第一区域,且与电子元件11电连接。无源元件是嵌设于介电基板,且至少部分设置于介电基板的第二区域。第二重布线层设置于介电基板的一表面,且第二重布线层是位于第一区域与第二区域,并且与无源元件15及电子元件11电连接。无源元件15的厚度大于电子元件11的厚度。
以下将示范性地说明图1所示的嵌入式封装结构1的制程步骤。请再参阅图2A至图2E,首先,如图2A所示,提供嵌入式封装结构1的一半封装结构,其中该半封装结构是先将电子元件11内埋于绝缘基板10内,并使多个导电通孔103及导电通孔104分别与绝缘基板10的顶面101及底面102上的第一导电层12及第二导电层13的对应的第一导电图形及第二导电图形连接而导通。接着,将第一绝缘材料14a覆盖部分绝缘基板10的顶面101以及覆盖第一导电层12的外侧面12a,且将第二绝缘材料14b覆盖部分绝缘基板10的底面102以及覆盖第二导电层13的外侧面13a。之后,于第一绝缘材料14a中形成多个导电通孔105,并使导电通孔105与第一导电层12的对应的第一导电图形连接而导通。接着,于第一绝缘材料14a的顶面141上形成第三导电层17,其中第三导电层17中对应的第三导电图形与对应的导电通孔105连接而导通。
接着,如图2B所示,利用例如但不限于激光穿孔方式穿透第一绝缘材料14a、绝缘基板10及第二绝缘材料14b而形成开槽15a。之后,如图2C所示,将无源元件15置入开槽15a中,其中当无源元件15置入开槽15a时,是先将导热胶带15b(thermal tape)贴附于第二绝缘材料14b的底面,并使无源元件15置入开槽15a时与导热胶带15b贴附连接。
然后,如图2D所示,将固着材料16填设于无源元件15与开槽15a的内壁之间的空隙,且部分覆盖于第一绝缘材料14a的顶面141、第三导电层17的外侧面17a及无源元件15的外侧面155,从而使无源元件15经由固着材料16的包覆而可固定于开槽15a内。之后,移除导热胶带15b。
最后,如图2E所示,将第四导电层18形成且设置于固着材料16的顶面161上,并使第四导电层18与对应的多个导电通道106连接而导通,从而完成图1所示的嵌入式封装结构1的制作。
本公开的嵌入式封装结构1的结构并不以前述实施例为限,以下将以图3至图5进一步说明本公开的嵌入式封装结构1的各种变化例,其中图3至图5中所示的嵌入式封装结构的整体结构及元件特征是相似于图1所示的嵌入式封装结构1,且相同元件符号代表相同的元件结构、连接关系及功用,于后不再赘述。
图3为本公开第二优选实施例的嵌入式封装结构的结构示意图。相较于图1所示的嵌入式封装结构1,本实施例的嵌入式封装结构3与图1所示的嵌入式封装结构1不同的处在于,本实施例的无源元件15是完全设置于开槽15a内,且无源元件15的顶面155是与第一绝缘材料14a的顶面齐平,并且无源元件15的第二导接端150是与对应的导电通道106连接而导通。此外,导电通孔105是连接于第一导电层12与对应的导电通道106之间。另外,嵌入式封装结构3包含第四绝缘材料14d、磁性元件15c及第五导电层20,而不具有第三导电层17及第四导电层18。其中,第四绝缘材料14d是设置于固着材料16的顶面161。磁性元件15c是埋设于第四绝缘材料14d中,并设置于固着材料16的顶面161上。第五导电层20是设置于第四绝缘材料14d的顶面143,且通过第五导电层20而暴露部分的第四绝缘材料14d的顶面143。
于本实施例中,第四绝缘材料14d还包含多个导电通孔107,多个导电通孔107的第一端是与固着材料16的对应的多个导电通道106连接而导通,多个导电通孔107的第二端与第五导电层20相连接而导通。相似地,第五导电层20以例如蚀刻方式形成一个或多个第五导电图形,因此第五导电层20的多个第五导电图形会与对应的多个导电通孔107的第二端连接而导通。
图4为本公开第三优选实施例的嵌入式封装结构的结构示意图。相较于图1所示的嵌入式封装结构1,本实施例的嵌入式封装结构4与图1所示的嵌入式封装结构1不同的处在于,本实施例的嵌入式封装结构4的无源元件15是完全内埋于绝缘基板10内,因此固着材料16仅部分覆盖于第一绝缘材料14a的顶面141。此外,多个导电通孔108位于绝缘基板10内,且多个导电通孔108的第一端是与第一导电层12连接。无源元件15具有多个第二导接端151,其中多个第二导接端151是与对应的导电通孔108的第二端连接而导通。相似地,本实施例的第一绝缘材料14a与图1所示的嵌入式封装结构1同样是具有多个导电通孔105,其中部分的导电通孔105是通过第一导电层12而与对应的导电通孔108连接而导通。相似地,本实施例的嵌入式封装结构4还包含第四绝缘材料14d、磁性元件15c及第五导电层20,而不具有第三导电层17及第四导电层18。第四绝缘材料14d、磁性元件15c及第五导电层20的设置方式与图3的嵌入式封装结构3的设置方式相同,差别仅是在于嵌入式封装结构4的磁性元件15c的厚度是实质上与嵌入式封装结构3的磁性元件15c的厚度相同。然而,嵌入式封装结构4的磁性元件15c的宽度是较宽于嵌入式封装结构3的磁性元件15c的宽度,其他部分于此不再赘述。
图5为本公开第四优选实施例的嵌入式封装结构的结构示意图。相较于图4所示的嵌入式封装结构4,本实施例的嵌入式封装结构5是利用半导体制程直接形成无源元件15,例如利用半导体制程将电容15d形成于绝缘基板10中,以及将电阻R形成于绝缘基板10上,其中电容15d的设置位置及方式与图4所示的无源元件15的设置位置及方式相同。电阻R是嵌设于第一绝缘材料14a中,且设置在绝缘基板10的顶面101上。此外,电阻R的导接端是与对应的导电通孔105连接而导通。另外,嵌入式封装结构5的第四绝缘材料14d、磁性元件15c及第五导电层20的设置方式与图4的嵌入式封装结构4的第四绝缘材料14d、磁性元件15c及第五导电层20的设置方式相同,于此不再赘述。
于一些实施例中,本公开的嵌入式封装结构1、3、4、5的整体厚度以小于1000μm为较佳,且以小于800μm为更佳,并以小于600μm为最佳。此外,由于电子元件与无源元件是以水平设置方式嵌设于绝缘基板内,因此有利于散热。
综上所述,本公开提供一种嵌入式封装结构,其是将电子元件与无源元件相隔离地嵌设于绝缘基板中,以使无源元件与电子元件水平设置而实现封装,藉此使嵌入式封装结构的整体厚度可以进一步地薄化,从而使嵌入式封装结构得以应用于超薄电子产品。此外,本公开的嵌入式封装结构的封装结构较为扁平薄化且易于制造,且具较高功率密度、较佳电气特性与热管理效能。
本公开得由本领域相关技术人员任施匠思而为诸般修饰,然皆不脱权利要求所欲保护者。
Claims (17)
1.一种嵌入式封装结构,包含:
一绝缘基板,具有至少一第一导电通孔及至少一第二导电通孔;
一第一导电层,设置于该绝缘基板的一顶面上,其中该第一导电层与该至少一第一导电通孔连接导通;
一第二导电层,设置于该绝缘基板的一底面上,其中该第二导电层与该至少一第二导电通孔连接导通;
一电子元件,内埋于该绝缘基板内,且具有多个第一导接端,其中该多个第一导接端是通过该至少一第一导电通孔及该至少一第二导电通孔而与该第一导电层及该第二导电层相导通;
一第一绝缘材料,覆盖于该第一导电层的一外侧面,且部分覆盖于该绝缘基板的该顶面;
一第二绝缘材料,覆盖于该第二导电层的一外侧面,且部分覆盖于该绝缘基板的该底面;
一无源元件,是隔离地设置于该电子元件的一第一侧边,其中该无源元件至少部分嵌设于该绝缘基板;
一开槽,邻设于该电子元件,其中该开槽是贯穿该第一绝缘材料、该第二绝缘材料及该绝缘基板,该无源元件是至少部分设置于该开槽中,且该开槽大于该无源元件,使该无源元件与该开槽的内壁间具有一空隙;
一固着材料,填设于该无源元件与该开槽的内壁间的该空隙,使该无源元件及该开槽之间通过该固着材料而相互黏着固设;
一第三绝缘材料,设置于该固着材料的一顶面;
一磁性元件,嵌设于该第三绝缘材料中且设置于该固着材料的该顶面上;以及
一第三导电层,设置于该第三绝缘材料的一顶面,其中部分的该第三绝缘材料的该顶面是通过该第三导电层而暴露,
其中该固着材料部分覆盖于该第一绝缘材料的一顶面及该无源元件的一顶面。
2.如权利要求1所述的嵌入式封装结构,其中该无源元件具有至少一第二导接端,且该无源元件与该电子元件是相互水平设置。
3.如权利要求2所述的嵌入式封装结构,其中该嵌入式封装结构还包含:
一第四导电层,设置于该第一绝缘材料的该顶面上,其中部分的该第一绝缘材料的该顶面是通过该第四导电层而暴露;以及
一第五导电层,设置于该固着材料的该顶面,且暴露部分的该固着材料的该顶面,
其中该固着材料部分覆盖于该第一绝缘材料的该顶面、该第四导电层的一外侧面及该无源元件的一外侧面。
4.如权利要求3所述的嵌入式封装结构,其中该固着材料还包含多个导电通道,该多个导电通道与该第四导电层及该无源元件的对应的第二导接端连接导通。
5.如权利要求4所述的嵌入式封装结构,其中该第五导电层是与该多个导电通道的多个顶面相连接。
6.如权利要求5所述的嵌入式封装结构,其中该第一绝缘材料还包含多个第三导电通孔,电连接于该第一导电层与该第四导电层之间,其中该电子元件的一上表面的该多个第一导接端通过对应的该第一导电通孔与对应的该第三导电通孔连接导通。
7.如权利要求2所述的嵌入式封装结构,其中该无源元件的该顶面是与该第一绝缘材料的该顶面齐平。
8.如权利要求7所述的嵌入式封装结构,其中该固着材料还包含多个导电通道,其中该多个导电通道与该无源元件的对应的该第二导接端连接导通。
9.如权利要求8所述的嵌入式封装结构,其中该第一绝缘材料包含多个第三导电通孔,其中该第一导电层通过对应的该第三导电通孔与对应的该导电通道电连接。
10.如权利要求9所述的嵌入式封装结构,其中该第三绝缘材料包含多个第四导电通孔,其中该第三导电层通过对应的该四导电通孔与对应的该导电通道电连接。
11.如权利要求2所述的嵌入式封装结构,其中该无源元件是完全嵌设于该绝缘基板内,且该无源元件具有多个第二导接端。
12.如权利要求11所述的嵌入式封装结构,其中该绝缘基板包含多个第三导电通孔,其中该第一导电层通过对应的该多个第三导电通孔与对应的该多个第二导接端电连接。
13.如权利要求12所述的嵌入式封装结构,其中该固着材料包含多个导电通道。
14.如权利要求13所述的嵌入式封装结构,其中该第一导电层通过该第一绝缘材料的多个第四导电通孔而与对应的该导电通道电连接。
15.如权利要求14所述的嵌入式封装结构,其中该第三导电层通过该第三绝缘材料的多个第五导电通孔而与对应的该导电通道电连接。
16.如权利要求15所述的嵌入式封装结构,其还包含一电阻,邻设于该电子元件的一第二侧边且设置于该绝缘基板的该顶面,其中该电阻是与对应的该第四导电通孔连接导通。
17.如权利要求1所述的嵌入式封装结构,其中该无源元件为一电容、一电阻或一电感。
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