JP2001507842A - チップカードに組み込む半導体チップのための支持エレメント - Google Patents
チップカードに組み込む半導体チップのための支持エレメントInfo
- Publication number
- JP2001507842A JP2001507842A JP52075299A JP52075299A JP2001507842A JP 2001507842 A JP2001507842 A JP 2001507842A JP 52075299 A JP52075299 A JP 52075299A JP 52075299 A JP52075299 A JP 52075299A JP 2001507842 A JP2001507842 A JP 2001507842A
- Authority
- JP
- Japan
- Prior art keywords
- support element
- connection
- semiconductor chip
- chip
- element according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Credit Cards Or The Like (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 特にチップカード内に組み込むための、少なくとも2つの接続部(1)を 有する半導体チップ(2)のための支持エレメントであって、半導体チップ(2 )を包囲して保護する包囲質量体(5)を有しており、接続部(1)が導電性の 材料から成っていて、互いに向き合った端部において減少せしめられた厚さを有 しており、その際この端部の横断面が単に一方の側においてだけ段を有しており 、半導体チップ(2)がこのわずかな厚さの区分(1a)の範囲内で接続部(1 )上に配置されかつ接続部と機械的に結合されている形式のものにおいて、接続 部(1)が包囲質量体(5)の主表面の一方において単に2つの互いに逆の側の 縁部に沿って配置されており、わずかな厚さの接続部端部(1a)が型押しによ って生ぜしめられていることを特徴とする、チップカード内に組み込む半導体チ ップのための支持エレメント。 2. 露出している接続部表面が包囲質量体(5)の表面と同一面を形成してい ることを特徴とする、請求項1記載の支持エレメント。 3. 接続部(1)が単に包囲質量体(5)の範囲内でだけ延びており、包囲質 量体の範囲内で接触面を形成していることを特徴とする、請求項1又は2記載の 支持エレメント。 4. 接続部(1)が包囲質量体(5)の縁部を越えて突出していて、接触面を 形成していることを特徴とする、請求項1又は2記載の支持エレメント。 5. 接触片(1)が幅を広げられた端部(1b)を有していることを特徴とす る、請求項4記載の支持エレメント。 6. 半導体チップ(2)がその回路構造を有している側を接続部(1)に向け て接続部上に配置されていることを特徴とする、請求項1から5までのいずれか 1項記載の支持エレメント。 7. 半導体チップ(2)が、接続部(1)の横断面段を有している側に配置さ れていることを特徴とする、請求項6記載の支持エレメント。 8. 機械的な結合部が電気的な接続部(6)としても機能することを特徴とす る、請求項7記載の支持エレメント。 9. 電気的な接続部がボンディングワイヤ(4)によって実現されていること を特徴とする、請求項7記載の支持エレメント。 10.半導体チップ(2)がその回路構造を有する側を接続部(1)から離れる 方向に向けて接続部(1)の横断面段を有する側に配置されていて、電気的な接 続部がボンディングワイヤ(4)によって実現されていることを特徴とする、請 求項1から5までのいずれか1項記載の支持エレメント。 11.接続部がほぼ直角に半導体チップ(2)に向かって折り曲げられているこ とを特徴とする、請求項1から10までのいずれか1項記載の支持エレメント。 12.接続部が、ほぼ直角の、半導体チップ(2)から離れる方向の別の折り曲 げ部を有していることを特徴とする、請求項11記載の支持エレメント。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19745648A DE19745648A1 (de) | 1997-10-15 | 1997-10-15 | Trägerelement für einen Halbleiterchip zum Einbau in Chipkarten |
DE19745648.0 | 1997-10-15 | ||
PCT/DE1998/002768 WO1999019832A1 (de) | 1997-10-15 | 1998-09-17 | Trägerelement für einen halbleiterchip zum einbau in chipkarten |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001507842A true JP2001507842A (ja) | 2001-06-12 |
JP3839063B2 JP3839063B2 (ja) | 2006-11-01 |
Family
ID=7845667
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52075299A Expired - Fee Related JP3839063B2 (ja) | 1997-10-15 | 1998-09-17 | チップカードに組み込む半導体チップのための支持エレメント |
Country Status (10)
Country | Link |
---|---|
US (1) | US6719205B1 (ja) |
EP (1) | EP0951692A1 (ja) |
JP (1) | JP3839063B2 (ja) |
KR (1) | KR20000069487A (ja) |
CN (1) | CN1122942C (ja) |
BR (1) | BR9806706A (ja) |
DE (1) | DE19745648A1 (ja) |
RU (1) | RU2216042C2 (ja) |
UA (1) | UA46136C2 (ja) |
WO (1) | WO1999019832A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006139772A (ja) * | 2004-11-12 | 2006-06-01 | Samsung Techwin Co Ltd | 極超短波用のラジオ周波数認識タグ及びその認識タグの製造方法 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19918852C1 (de) * | 1999-04-26 | 2000-09-28 | Giesecke & Devrient Gmbh | Chipkarte mit Flip-Chip und Verfahren zu ihrer Herstellung |
DE19940564C2 (de) | 1999-08-26 | 2002-03-21 | Infineon Technologies Ag | Chipkartenmodul und diesen umfassende Chipkarte, sowie Verfahren zur Herstellung des Chipkartenmoduls |
DE19955537B4 (de) * | 1999-11-18 | 2006-04-13 | Orga Kartensysteme Gmbh | Verfahren zur Herstellung eines Trägerelementes für einen IC-Baustein |
DE60144452D1 (de) * | 2000-02-22 | 2011-05-26 | Toray Eng Co Ltd | Verfahren zur Herstellung einer kontaktlosen ID Karte |
SG106050A1 (en) * | 2000-03-13 | 2004-09-30 | Megic Corp | Method of manufacture and identification of semiconductor chip marked for identification with internal marking indicia and protection thereof by non-black layer and device produced thereby |
US6606247B2 (en) | 2001-05-31 | 2003-08-12 | Alien Technology Corporation | Multi-feature-size electronic structures |
US7253735B2 (en) | 2003-03-24 | 2007-08-07 | Alien Technology Corporation | RFID tags and processes for producing RFID tags |
FR2857483B1 (fr) * | 2003-07-11 | 2005-10-07 | Oberthur Card Syst Sa | Carte a puce anti-intrusion |
FR2869706B1 (fr) * | 2004-04-29 | 2006-07-28 | Oberthur Card Syst Sa | Entite electronique securisee, telle qu'un passeport. |
JP2008504627A (ja) * | 2004-06-30 | 2008-02-14 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | ホルダ挿入用チップカード |
CN101002218B (zh) * | 2004-07-29 | 2010-05-12 | Nxp股份有限公司 | 具有应变消除装置的模块基本单元 |
US7688206B2 (en) | 2004-11-22 | 2010-03-30 | Alien Technology Corporation | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
FR2888371B1 (fr) * | 2005-07-06 | 2007-10-05 | Oberthur Card Syst Sa | Support de donnees pliable a puce sans contact tel qu'un passeport |
US8608080B2 (en) | 2006-09-26 | 2013-12-17 | Feinics Amatech Teoranta | Inlays for security documents |
EP2070016B1 (en) * | 2006-09-26 | 2011-01-19 | Féinics AmaTech Teoranta | Method of connecting an antenna to a transponder chip and corresponding inlay substrate |
US7707706B2 (en) * | 2007-06-29 | 2010-05-04 | Ruhlamat Gmbh | Method and arrangement for producing a smart card |
DE102008016274A1 (de) * | 2008-03-28 | 2009-10-01 | Smartrac Ip B.V. | Chipträger für ein Transpondermodul sowie Transpondermodul |
DE102010041917B4 (de) * | 2010-10-04 | 2014-01-23 | Smartrac Ip B.V. | Schaltungsanordnung und Verfahren zu deren Herstellung |
CN114823550B (zh) * | 2022-06-27 | 2022-11-11 | 北京升宇科技有限公司 | 一种适于批量生产的芯片封装结构及封装方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3019207A1 (de) * | 1980-05-20 | 1981-11-26 | GAO Gesellschaft für Automation und Organisation mbH, 8000 München | Traegerelement fuer einen ic-chip |
DE3123198C2 (de) * | 1980-12-08 | 1993-10-07 | Gao Ges Automation Org | Trägerelemente für einen IC-Baustein |
DE3248385A1 (de) * | 1982-12-28 | 1984-06-28 | GAO Gesellschaft für Automation und Organisation mbH, 8000 München | Ausweiskarte mit integriertem schaltkreis |
JPH02303056A (ja) * | 1989-05-17 | 1990-12-17 | Mitsubishi Electric Corp | 半導体集積回路の製造方法 |
FR2659157B2 (fr) | 1989-05-26 | 1994-09-30 | Lemaire Gerard | Procede de fabrication d'une carte dite carte a puce, et carte obtenue par ce procede. |
JPH04148999A (ja) * | 1990-10-12 | 1992-05-21 | Dainippon Printing Co Ltd | Icカード |
US5172214A (en) * | 1991-02-06 | 1992-12-15 | Motorola, Inc. | Leadless semiconductor device and method for making the same |
KR930014916A (ko) * | 1991-12-24 | 1993-07-23 | 김광호 | 반도체 패키지 |
DE19527359A1 (de) * | 1995-07-26 | 1997-02-13 | Giesecke & Devrient Gmbh | Schaltungseinheit und Verfahren zur Herstellung einer Schaltungseinheit |
DE19532755C1 (de) * | 1995-09-05 | 1997-02-20 | Siemens Ag | Chipmodul, insbesondere für den Einbau in Chipkarten, und Verfahren zur Herstellung eines derartigen Chipmoduls |
FR2741191B1 (fr) * | 1995-11-14 | 1998-01-09 | Sgs Thomson Microelectronics | Procede de fabrication d'un micromodule, notamment pour cartes a puces |
KR0179925B1 (ko) * | 1996-06-14 | 1999-03-20 | 문정환 | 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지 |
DE29621837U1 (de) * | 1996-12-16 | 1997-02-27 | Siemens AG, 80333 München | Trägerelement für Halbleiterchips |
US6049463A (en) * | 1997-07-25 | 2000-04-11 | Motorola, Inc. | Microelectronic assembly including an antenna element embedded within a polymeric card, and method for forming same |
-
1997
- 1997-10-15 DE DE19745648A patent/DE19745648A1/de not_active Withdrawn
-
1998
- 1998-09-17 EP EP98956777A patent/EP0951692A1/de not_active Withdrawn
- 1998-09-17 KR KR1019997005344A patent/KR20000069487A/ko not_active Application Discontinuation
- 1998-09-17 UA UA99063283A patent/UA46136C2/uk unknown
- 1998-09-17 CN CN98802532A patent/CN1122942C/zh not_active Expired - Fee Related
- 1998-09-17 BR BR9806706-0A patent/BR9806706A/pt not_active IP Right Cessation
- 1998-09-17 WO PCT/DE1998/002768 patent/WO1999019832A1/de not_active Application Discontinuation
- 1998-09-17 RU RU99115169/09A patent/RU2216042C2/ru not_active IP Right Cessation
- 1998-09-17 JP JP52075299A patent/JP3839063B2/ja not_active Expired - Fee Related
-
1999
- 1999-06-15 US US09/333,322 patent/US6719205B1/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006139772A (ja) * | 2004-11-12 | 2006-06-01 | Samsung Techwin Co Ltd | 極超短波用のラジオ周波数認識タグ及びその認識タグの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
RU2216042C2 (ru) | 2003-11-10 |
CN1247616A (zh) | 2000-03-15 |
US6719205B1 (en) | 2004-04-13 |
CN1122942C (zh) | 2003-10-01 |
DE19745648A1 (de) | 1998-11-26 |
BR9806706A (pt) | 2000-04-04 |
EP0951692A1 (de) | 1999-10-27 |
UA46136C2 (uk) | 2002-05-15 |
JP3839063B2 (ja) | 2006-11-01 |
KR20000069487A (ko) | 2000-11-25 |
WO1999019832A1 (de) | 1999-04-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2001507842A (ja) | チップカードに組み込む半導体チップのための支持エレメント | |
JP2757309B2 (ja) | Icカードの構造 | |
JP4475160B2 (ja) | 電子装置の製造方法 | |
JP2008234686A (ja) | チップカード及びその製造方法 | |
JP5673585B2 (ja) | コイル部品 | |
JPH0630985B2 (ja) | 支持体に集積回路を取り付ける方法、集積回路を支持する装置及び超小型電子回路装置を備えるカード | |
JP2682936B2 (ja) | 半導体装置 | |
JPH054914B2 (ja) | ||
US6031724A (en) | IC card and method of manufacturing the same | |
RU2328840C2 (ru) | Способ монтажа электронного компонента на подложке | |
CN107111779B (zh) | 包括互连区的单面电子模块的制造方法 | |
US7208822B1 (en) | Integrated circuit device, electronic module for chip cards using said device and method for making same | |
JP2856642B2 (ja) | 半導体装置及びその製造方法 | |
JP2001177005A (ja) | 半導体装置及びその製造方法 | |
JP2786979B2 (ja) | 固体電解コンデンサ | |
KR100610144B1 (ko) | 플립 칩 조립 구조를 가지는 칩-온-보드 패키지의 제조 방법 | |
JP3878450B2 (ja) | コンビネーション型icカード及びその製造方法 | |
JP3877988B2 (ja) | 半導体装置 | |
JPH06511581A (ja) | 電子ラベル | |
JPH11219419A (ja) | Icカード及びその製造方法 | |
JP3958451B2 (ja) | アンテナコイル付icカード | |
US6239967B1 (en) | Electronic assembly including an electronic unit connected to a coil | |
JP2002207982A (ja) | 接触非接触両用icモジュール及びicカード | |
JPWO2005027028A1 (ja) | メモリパック | |
JP3170519B2 (ja) | メモリカード |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040601 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040818 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20050705 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20051003 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20051117 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060308 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060515 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060712 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060802 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |