CN1122942C - 用于芯片卡内安装的半导体芯片的载体元件 - Google Patents
用于芯片卡内安装的半导体芯片的载体元件 Download PDFInfo
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- CN1122942C CN1122942C CN98802532A CN98802532A CN1122942C CN 1122942 C CN1122942 C CN 1122942C CN 98802532 A CN98802532 A CN 98802532A CN 98802532 A CN98802532 A CN 98802532A CN 1122942 C CN1122942 C CN 1122942C
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Abstract
本发明涉及具有至少两个接线片(1)的半导体芯片(2)的载体元件,尤其是用于在芯片卡内安装的载体元件,该载体元件具有保护半导体芯片(2)的包封材料(5)。接线片(1)安置在仅沿着两个对置边缘的包封材料(5)的主平面之一上。它们由导电材料制成并且在彼此面对的两末端(1a)上具有减小的厚度,其中截面只在一侧具有一个阶梯。半导体芯片(2)安置在接线片(1)上的厚度减小的该段(1a)的范围内并且与其机械连接。
Description
技术领域
本发明涉及具有至少两个接线片的半导体芯片的载体元件,尤其是用于芯片卡内安装的载体元件,其中该元件具有包围和保护半导体芯片的包封材料,该接线片由导电材料制成并在彼此面对的末端上具有较小的厚度,其中截面只在一侧具有一阶梯。半导体芯片安置在厚度较小部位的接线片上并且与其机械连接。
背景技术
这种载体元件已由JP08-116016A日本专利文摘获悉。然而这种公知的载体元件并不适合在芯片卡内安装,因为它在两侧装配包封材料并且接线片是不能以适用方式接近的。
用于芯片卡内安装的半导体芯片的载体元件以各种方式为大家所公知。US5,134,773公开了具有以所谓引线框形式由导电材料制成的接触面的载体元件,其中半导体芯片粘接在当中安排的芯片岛上,并且借助压焊丝与外围安排的接触面电连接。半导体芯片被保护它的和压焊丝的包封材料所包围,此外包封材料使接触面保持在其位置上。因为从远离芯片一侧接触面必须是可以自由接近的,所以包封材料只在一侧存在。为了仍然提供好的机械支撑,在远离芯片一侧与其彼此电绝缘的隙缝区域内的接触面具有侧凹,该侧凹被保护罩填满,并用一种铆接。
虽然在US5,134,773描述的载体元件是为所谓有接触的芯片卡设计的,即:它具有位于芯片卡表面的、从外部对读出设备可接近的接触面,然而它是轻而易举地可能的而且也是公知的,只提供两个接线片,该接线片可与卡片内或在卡片镶嵌物上安置的线圈电连接。
此外,接线片在数目和布局方面可以如此配备,使得它们能够以相同方式既适合于与线圈或天线连接也适合于与读出设备连接。
在用分层技术制造无接触芯片卡时,这意味着:载体元件安装其上的线圈支撑膜片用至少两个保护膜片熔接,关键是需夹入层内的、被看作外部物体的载体元件,几何上设计得尽可能如此之小,以便在载体元件周围实现在温度和压力作用下变软的保护膜片的最佳环流,由此完成高质量的卡片而无缩孔和印刷图象消失,即为追加的印刷实现平整的表面。
无接触应用芯片卡的典型结构如下组成:线圈支撑膜片具有约200μm厚度,两核心膜片(kernfolie)具有各约100μm的厚度,在两侧的两印刷膜片具有各约150μm的厚度,两个划伤防护膜片具有各约50μm的厚度,根据ISO标准7816合在一起得约800μm的厚度。由此得出必要的载体元件高度小于400μm以及在卡片平面内尽可能小的膨胀延伸。
在实现由US5,134,773公知的载体元件时,根据芯片安装在芯片岛加上压焊丝的弧线高度得出大于400μm的高度。
发明内容
本发明的任务是:提供具有较小高度、改善断裂特性以及能容易制造的载体元件。
本任务通过以下的载体元件得以解决。
半导体芯片用的载体元件,该载体元件具有至少两个接线片、尤其适于装入芯片卡,具有以下标志:
-元件具有包围和保护半导体芯片的包封材料,
-接线片由导电材料制成且在彼此面对的末端上有减小的厚度,其中剖面只在一侧有一阶梯,
-半导体芯片安置在接线片上减小厚度一段的区域内并与其机械连接。其特征为如下标志:
-接线片沿着仅有的两彼此相对的边缘安置在包封材料的主平面之一上,
-具有减小厚度的接线片末端由冲压产生。
本发明还包括基于上述特征的载体元件的有益发展。
作为在装配半导体芯片、包围芯片以及连接线时的支撑框部件,即所谓引线框部件的接线片具有如此减小厚度的一段,以致于其截面(仅在一侧)具有一阶梯。按照本发明所示方式减小厚度的这一段通过冲压制造。因此就大多数情况而言降低厚度到额定接线片厚度的50%是足够的。
这意味着,接线片的主平面是平的,而对置的表面有一阶梯。半导体芯片安置在这段区域内。这时它能够安置在阶梯一侧或与其对置的一侧上。当它安置在接线片的阶梯一侧时,芯片以其有源一侧面向离开接线片的方向装配是有益的。当它安置在与阶梯侧对置的一侧上时,则具有优点为:芯片以其有源一侧面向接线片的方向装配,因为这时处于厚度减小的一段区域内的压焊线可以与接线片连接,并因此压焊线的弧线高度不再起重要性作用。在两种情况下均可获得所希望的高度的减小。
尽可能多的减小高度是通过所谓的倒装片装配而实现的,在倒装片装配时半导体芯片用其焊接垫直接焊接或粘接在接线片上,该焊接垫以有利的方式提供加高的所谓“突起物”。因此能够放弃用压焊线。
放弃芯片岛不仅具有减少载体元件厚度的优点而且具有改进包封材料与接线片固定的优点,因为包封材料能从两侧包围芯片,并且形成从芯片到接线片很好的连接。通过取消芯片岛也不再出现缺口作用力,所以导致更佳的断裂强度特性。
根据所希望的载体元件较小高度,接线片表面之一将暴露在外并将提供接触使用。由于位于接线片之间的包封材料与接线片表面对准是有优点的,因此可以尽可能好地被装入芯片卡内,尤其是装入分层的芯片卡内。
接线片可以向外突出到包封材料尺寸之外,并在那里形成用于与天线接线连接的接触片。这对于把天线线圈安置在支撑膜上的装配是具有优点的。支撑膜以有利方式具有空隙或凹槽(包封材料将处于其中),而接线片或在这种情况下的接触片则位于线圈支撑膜上的线圈接触片上。
然而只在包封材料的范围内提供接线片也是可能的,其优点为:这样的载体元件也能随后插入已分层的、当然有空隙的卡内。天线线圈末端合适地处于该空隙内,以便能够以简单的方式例如通过粘接或焊接或通过弹生连接部件与载体元件接线片连接。
只不过具有这样一种接触面来取代突出到边缘之外的接触片的载体元件,也可以直接安放在线圈支撑膜片上。在这种情形下,卡的层压塑料的相应的核心膜片应具有一空隙。
接触片以有利方式可以具有一加宽的末端,以便能更好地与所绕线圈的接线片连接。
当接线片以直角弯向芯片,因而弯角区域处于包封材料内时,用接触片可实现包封材料的特佳的固定。当接线片再次以直角,最好向另一方向弯曲时,则可得到更进一步改善的固定。此外,按照这种方式产生可适用于另一可选择装配的其它的接触面。
附图说明
本发明下面依靠实施例借助附图详细说明。其中这些附图分别示出:
图1-6示出本发明载体元件的各种实施例的剖面图。
图7示出具有用于在线圈支撑膜片上装配的接触片的载体元件,
图8示出具有用于在线圈支撑膜片上或直接在芯片卡内装配的接触面的载体元件。
具体实施方式
图1示出本发明载体元件剖面图,正如图7所画出的那样。两接线片1沿着载体元件对置的边缘上安置。一方面它们作为半导体芯片2的支承面,另一方面它们用作从载体元件外与半导体芯片2接触。为此目的,它们经过压焊线4与半导体芯片2连接。半导体芯片2用粘接剂3与接线片1机械连接。半导体芯片2和压焊线4用包封材料5浇注或挤压包封。保封材料5有利地具有明亮色彩,该色彩,并非像市场上一般可购得的深黑色物质那样,可通过芯片卡的膜层透光。
正如在图7所看到的那样,接线片1以有利方式安置在载体元件对角区内,以便在装配时为半导体芯片2提供均匀和均衡的衬底。为了装配的目的,接线片1与支持它的框架(所谓引线框)连接,并且在装配芯片、挤压包封或浇注之后,由框架中对接线片冲边成形。在列举的例子中只配置了两只接线片1,因为该载体元件主要适用于无接触芯片卡。然而根据ISO-标准7816毫无问题地可提供多个接线片作为接触面,以便按照这种方式得到接触式芯片卡的载体元件。主要的是不存在芯片岛。由此一方面避免了缺口作用力,另一方面包封材料5可以包围整个芯片2,所以可以更好地实现接线片1在载体元件上的粘着,因为它大部分通过粘接3保持着,不只依靠包封材料5和接线片1之间的粘附力。
当接线片1弯一角度,如图2所示,则可实现接线片更好的固定。接线片1的第一段1C以大体呈直角向芯片2弯曲。在继续成形中第二段1d也可以大体呈直角向另一方向弯曲。由此形成另一从外侧可接近的接触面,所以这样的载体元件也适用于所谓的组合卡,因为它从一侧可与线圈连接,而从另一侧能够通过读出装置接触。然而为此必须多于两个接触片。当然,只需两次弯角已足够用。
除了缺少芯片岛之外,应该看到本发明的载体元件的主要方面在接线片1的一段1a上,该段对额定厚度而言有一减小厚度,其中只在接线片1的一侧上有载面呈阶梯的一段。当半导体芯片2放置在具有减小厚度的这段1a范围内时,则因此载体元件的总高度可以降低约为接线片厚度的一半。因为这段1a可以保持短小,所以接线片1的机械特性不受影响。
在图1和图2,半导体芯片2安置在接线片1载面阶梯的侧面上,其中半导体芯片2的有源侧面,即具有集成电路的一侧面向离开接线片1的方向。图3和图4示出另外一些方案,在该方案内半导体芯片2安置在接线片1面对截面阶梯的一侧上,其中有源的一侧面向接线片1的方向。这时压焊线4按照本发明方式引到具有减小厚度的一段1a上,所以不必因压焊线的弧线高度提供载体元件的附加高度。当芯片背面未配置包封材料5(如图4所示)时,能达到进一步减小高度。这是可能的,因为半导体芯片2的有源一侧面向接线片1的方向。
图5和图6示出另外一些装配方案,其中半导体芯片2用所谓倒装片技术与接线片1连接。这时芯片2的接线垫直接与具有减小厚度的接线片段相连。它可以事先提供导电的隆起物6,所谓的“突出物”或焊接峰点。图6的载体元件具有最小高度,其中半导体芯片2用倒装片技术安装在具有减小厚度1a的一段范围内,而且芯片背面保持未被包封材料5所覆盖。
图7示出把本发明的载体元件装入到天线线圈8用的支撑膜片7内的一个可能方案。该载体元件配备带有接触片的接线片1,那就是说配备向包封材料5边缘之外突出的接线片1。接触片具有加宽的末端1b,为了实现与线圈接线片10更好接触。在装配时包封材料5放入支撑膜片7的空隙9内,其中接触片1与线圈接线片10接触。这种装配方案实现把载体元件特别平整地装入分层的卡内。
图8示出一种方案,在该方案中接线片1作为接触面(在图中不应该看到,因为它处于载体元件的下侧)形成。这表示突出在包封材料5的边缘之外的一段,例如在冲制时已从引线框除去。载体元件放置到线圈支撑膜7上,并且与线圈接线片10接触。为了得到平整的芯片卡表面,芯片卡层压塑料片的上部核心膜片必须具有空隙。
载体元件的这种实施形式当然也可以事后装入已经层压或甚至浇注的卡11内,为此该卡11具有空隙12。在空隙12内应该可以看到线圈接线片10,该线圈接线片10通过这优越的设计实现与载体元件接线片1的简单接触。
这种事后把载体元件装入芯片卡11可以实现以简单方式制造所谓的组合卡,该组合卡一方面具有用于与读出装置接触的接触面,这些接触面处在芯片卡11的一个表面上,另一方面含有线圈8。图2的载体元件特别适合于它。
Claims (12)
1.半导体芯片(2)用的载体元件,该载体元件具有至少两个接线片(1)、尤其适于装入芯片卡(11),具有以下标志:
-元件具有包围和保护半导体芯片(2)的包封材料(5),
-接线片(1)由导电材料制成且在彼此面对的末端(1a)上有减小的厚度,其中剖面只在一侧有一阶梯,
-半导体芯片(2)安置在接线片(1)上减小厚度一段的区域内并与其机械连接。其特征为如下标志:
-接线片(1)沿着仅有的两彼此相对的边缘安置在包封材料(5)的主平面之一上,
-具有减小厚度的接线片末端(1a)由冲压产生。
2.根据权利要求1所述的载体元件,其特征为:暴露出的接线片表面与包封材料(5)的表面对准。
3.根据权利要求1或2所述的载体元件,其特征为:接线片(1)只在包封材料(5)范围内伸展并在那里形成接触面。
4.根据权利要求1或2所述的载体元件,其特征为:接线片(1)向包封材料(5)的边缘之外突出并形成接触片。
5.根据权利要求4所述的载体元件,其特征为:接触片(1)具有加宽的末端(1b)。
6.根据权利要求1或2所述的载体元件,其特征为:半导体芯片(2)以其具有电路结构的一侧,面向接线片(1)安置在此接线片上。
7.根据权利要求6所述的载体元件,其特征为:半导体芯片(2)安置在接线片(1)具有截面阶梯的一侧上。
8.根据权利要求7所述的载体元件,其特征为:所述接线片由导电材料制成,由此机械连接也起着电连接(6)的作用。
9.根据权利要求7所述的载体元件,其特征为:电连接通过压焊线(4)实现。
10.根据权利要求1或2所述的载体元件,其特征为:半导体芯片(2)以其具有电路结构的一侧,面向离开接线片(1)的方向安置在接线片(1)具有载面阶梯一侧上,并且电连接通过压焊线(4)实现。
11.根据权利要求1或2所述的载体元件,其特征为:接线片以大体呈直角向半导体芯片(2)弯曲。
12.根据权要求11所述的载体元件,其特征为:接线片具有离半导体芯片(2)弯曲的大体呈直角的另一弯角。
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Application Number | Priority Date | Filing Date | Title |
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DE19745648A DE19745648A1 (de) | 1997-10-15 | 1997-10-15 | Trägerelement für einen Halbleiterchip zum Einbau in Chipkarten |
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CN1247616A CN1247616A (zh) | 2000-03-15 |
CN1122942C true CN1122942C (zh) | 2003-10-01 |
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Country Status (10)
Country | Link |
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US (1) | US6719205B1 (zh) |
EP (1) | EP0951692A1 (zh) |
JP (1) | JP3839063B2 (zh) |
KR (1) | KR20000069487A (zh) |
CN (1) | CN1122942C (zh) |
BR (1) | BR9806706A (zh) |
DE (1) | DE19745648A1 (zh) |
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FR2888371B1 (fr) * | 2005-07-06 | 2007-10-05 | Oberthur Card Syst Sa | Support de donnees pliable a puce sans contact tel qu'un passeport |
US8608080B2 (en) | 2006-09-26 | 2013-12-17 | Feinics Amatech Teoranta | Inlays for security documents |
WO2008037579A1 (en) * | 2006-09-26 | 2008-04-03 | Advanced Micromechanic And Automation Technology Ltd | Method of connecting an antenna to a transponder chip and corresponding inlay substrate |
US7707706B2 (en) * | 2007-06-29 | 2010-05-04 | Ruhlamat Gmbh | Method and arrangement for producing a smart card |
DE102008016274A1 (de) * | 2008-03-28 | 2009-10-01 | Smartrac Ip B.V. | Chipträger für ein Transpondermodul sowie Transpondermodul |
DE102010041917B4 (de) * | 2010-10-04 | 2014-01-23 | Smartrac Ip B.V. | Schaltungsanordnung und Verfahren zu deren Herstellung |
CN114823550B (zh) * | 2022-06-27 | 2022-11-11 | 北京升宇科技有限公司 | 一种适于批量生产的芯片封装结构及封装方法 |
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DE3019207A1 (de) * | 1980-05-20 | 1981-11-26 | GAO Gesellschaft für Automation und Organisation mbH, 8000 München | Traegerelement fuer einen ic-chip |
DE3123198C2 (de) * | 1980-12-08 | 1993-10-07 | Gao Ges Automation Org | Trägerelemente für einen IC-Baustein |
DE3248385A1 (de) * | 1982-12-28 | 1984-06-28 | GAO Gesellschaft für Automation und Organisation mbH, 8000 München | Ausweiskarte mit integriertem schaltkreis |
JPH02303056A (ja) * | 1989-05-17 | 1990-12-17 | Mitsubishi Electric Corp | 半導体集積回路の製造方法 |
FR2659157B2 (fr) | 1989-05-26 | 1994-09-30 | Lemaire Gerard | Procede de fabrication d'une carte dite carte a puce, et carte obtenue par ce procede. |
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KR930014916A (ko) * | 1991-12-24 | 1993-07-23 | 김광호 | 반도체 패키지 |
DE19527359A1 (de) * | 1995-07-26 | 1997-02-13 | Giesecke & Devrient Gmbh | Schaltungseinheit und Verfahren zur Herstellung einer Schaltungseinheit |
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FR2741191B1 (fr) * | 1995-11-14 | 1998-01-09 | Sgs Thomson Microelectronics | Procede de fabrication d'un micromodule, notamment pour cartes a puces |
DE29621837U1 (de) * | 1996-12-16 | 1997-02-27 | Siemens AG, 80333 München | Trägerelement für Halbleiterchips |
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US6049463A (en) * | 1997-07-25 | 2000-04-11 | Motorola, Inc. | Microelectronic assembly including an antenna element embedded within a polymeric card, and method for forming same |
-
1997
- 1997-10-15 DE DE19745648A patent/DE19745648A1/de not_active Withdrawn
-
1998
- 1998-09-17 JP JP52075299A patent/JP3839063B2/ja not_active Expired - Fee Related
- 1998-09-17 RU RU99115169/09A patent/RU2216042C2/ru not_active IP Right Cessation
- 1998-09-17 WO PCT/DE1998/002768 patent/WO1999019832A1/de not_active Application Discontinuation
- 1998-09-17 BR BR9806706-0A patent/BR9806706A/pt not_active IP Right Cessation
- 1998-09-17 UA UA99063283A patent/UA46136C2/uk unknown
- 1998-09-17 CN CN98802532A patent/CN1122942C/zh not_active Expired - Fee Related
- 1998-09-17 EP EP98956777A patent/EP0951692A1/de not_active Withdrawn
- 1998-09-17 KR KR1019997005344A patent/KR20000069487A/ko not_active Application Discontinuation
-
1999
- 1999-06-15 US US09/333,322 patent/US6719205B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
RU2216042C2 (ru) | 2003-11-10 |
BR9806706A (pt) | 2000-04-04 |
DE19745648A1 (de) | 1998-11-26 |
JP3839063B2 (ja) | 2006-11-01 |
JP2001507842A (ja) | 2001-06-12 |
US6719205B1 (en) | 2004-04-13 |
UA46136C2 (uk) | 2002-05-15 |
CN1247616A (zh) | 2000-03-15 |
KR20000069487A (ko) | 2000-11-25 |
WO1999019832A1 (de) | 1999-04-22 |
EP0951692A1 (de) | 1999-10-27 |
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