JP2001068652A5 - - Google Patents
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- Publication number
- JP2001068652A5 JP2001068652A5 JP1999244018A JP24401899A JP2001068652A5 JP 2001068652 A5 JP2001068652 A5 JP 2001068652A5 JP 1999244018 A JP1999244018 A JP 1999244018A JP 24401899 A JP24401899 A JP 24401899A JP 2001068652 A5 JP2001068652 A5 JP 2001068652A5
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- forming
- semiconductor substrate
- formation region
- active region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 230000015572 biosynthetic process Effects 0.000 claims description 28
- 238000005755 formation reaction Methods 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 19
- 230000002093 peripheral Effects 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 241000293849 Cordylanthus Species 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 2
- 230000035515 penetration Effects 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24401899A JP4270670B2 (ja) | 1999-08-30 | 1999-08-30 | 半導体装置及び不揮発性半導体記憶装置の製造方法 |
US09/521,969 US6281050B1 (en) | 1999-03-15 | 2000-03-09 | Manufacturing method of a semiconductor device and a nonvolatile semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24401899A JP4270670B2 (ja) | 1999-08-30 | 1999-08-30 | 半導体装置及び不揮発性半導体記憶装置の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2001068652A JP2001068652A (ja) | 2001-03-16 |
JP2001068652A5 true JP2001068652A5 (zh) | 2005-06-09 |
JP4270670B2 JP4270670B2 (ja) | 2009-06-03 |
Family
ID=17112495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24401899A Expired - Fee Related JP4270670B2 (ja) | 1999-03-15 | 1999-08-30 | 半導体装置及び不揮発性半導体記憶装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4270670B2 (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100350055B1 (ko) * | 1999-12-24 | 2002-08-24 | 삼성전자 주식회사 | 다중 게이트 절연막을 갖는 반도체소자 및 그 제조방법 |
KR20020091982A (ko) * | 2001-06-01 | 2002-12-11 | 삼성전자 주식회사 | 얕은 트렌치 소자분리 구조를 가지는 비휘발성 메모리소자 및 그 제조방법 |
JP4859290B2 (ja) * | 2001-06-21 | 2012-01-25 | 富士通セミコンダクター株式会社 | 半導体集積回路装置の製造方法 |
JP4672197B2 (ja) * | 2001-07-04 | 2011-04-20 | 株式会社東芝 | 半導体記憶装置の製造方法 |
KR100426485B1 (ko) * | 2001-12-22 | 2004-04-14 | 주식회사 하이닉스반도체 | 플래쉬 메모리 셀의 제조 방법 |
KR100466189B1 (ko) * | 2002-06-04 | 2005-01-13 | 주식회사 하이닉스반도체 | 플래시 메모리 셀의 제조 방법 |
KR100466195B1 (ko) * | 2002-07-18 | 2005-01-13 | 주식회사 하이닉스반도체 | 플래시 메모리 제조방법 |
JP2004095886A (ja) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
KR100481862B1 (ko) * | 2002-09-19 | 2005-04-11 | 삼성전자주식회사 | 스플리트 게이트형 플래시 메모리 소자의 제조방법 |
KR100642901B1 (ko) * | 2003-10-22 | 2006-11-03 | 매그나칩 반도체 유한회사 | 비휘발성 메모리 소자의 제조 방법 |
US7539963B2 (en) | 2003-10-24 | 2009-05-26 | Fujitsu Microelectronics Limited | Semiconductor device group and method for fabricating the same, and semiconductor device and method for fabricating the same |
JP4836416B2 (ja) * | 2004-07-05 | 2011-12-14 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US7205630B2 (en) * | 2004-07-12 | 2007-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for a semiconductor device having low and high voltage transistors |
JP2006156471A (ja) | 2004-11-25 | 2006-06-15 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
US7202125B2 (en) * | 2004-12-22 | 2007-04-10 | Sandisk Corporation | Low-voltage, multiple thin-gate oxide and low-resistance gate electrode |
JP5239254B2 (ja) * | 2007-08-22 | 2013-07-17 | サンケン電気株式会社 | 絶縁ゲート型半導体素子の製造方法 |
JP2009188196A (ja) * | 2008-02-06 | 2009-08-20 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2014229665A (ja) * | 2013-05-20 | 2014-12-08 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US10083878B1 (en) * | 2017-06-05 | 2018-09-25 | Globalfoundries Inc. | Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile |
JP2021048323A (ja) | 2019-09-19 | 2021-03-25 | キオクシア株式会社 | 半導体装置 |
CN116403970B (zh) * | 2023-06-09 | 2023-08-25 | 合肥晶合集成电路股份有限公司 | 半导体器件及其制造方法 |
-
1999
- 1999-08-30 JP JP24401899A patent/JP4270670B2/ja not_active Expired - Fee Related
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