JP2000332593A5 - - Google Patents

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Publication number
JP2000332593A5
JP2000332593A5 JP1999141250A JP14125099A JP2000332593A5 JP 2000332593 A5 JP2000332593 A5 JP 2000332593A5 JP 1999141250 A JP1999141250 A JP 1999141250A JP 14125099 A JP14125099 A JP 14125099A JP 2000332593 A5 JP2000332593 A5 JP 2000332593A5
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JP
Japan
Prior art keywords
feedback
delay
pch transistor
gate
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1999141250A
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English (en)
Japanese (ja)
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JP4101973B2 (ja
JP2000332593A (ja
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Application filed filed Critical
Priority to JP14125099A priority Critical patent/JP4101973B2/ja
Priority claimed from JP14125099A external-priority patent/JP4101973B2/ja
Priority to US09/421,932 priority patent/US6586973B2/en
Publication of JP2000332593A publication Critical patent/JP2000332593A/ja
Publication of JP2000332593A5 publication Critical patent/JP2000332593A5/ja
Application granted granted Critical
Publication of JP4101973B2 publication Critical patent/JP4101973B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP14125099A 1999-05-21 1999-05-21 出力バッファ回路 Expired - Fee Related JP4101973B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP14125099A JP4101973B2 (ja) 1999-05-21 1999-05-21 出力バッファ回路
US09/421,932 US6586973B2 (en) 1999-05-21 1999-10-21 Output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14125099A JP4101973B2 (ja) 1999-05-21 1999-05-21 出力バッファ回路

Publications (3)

Publication Number Publication Date
JP2000332593A JP2000332593A (ja) 2000-11-30
JP2000332593A5 true JP2000332593A5 (https=) 2006-06-15
JP4101973B2 JP4101973B2 (ja) 2008-06-18

Family

ID=15287575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14125099A Expired - Fee Related JP4101973B2 (ja) 1999-05-21 1999-05-21 出力バッファ回路

Country Status (2)

Country Link
US (1) US6586973B2 (https=)
JP (1) JP4101973B2 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3667690B2 (ja) 2001-12-19 2005-07-06 エルピーダメモリ株式会社 出力バッファ回路及び半導体集積回路装置
US7199616B2 (en) * 2004-11-29 2007-04-03 Exar Corporation Method and apparatus to generate break before make signals for high speed TTL driver
US7176743B2 (en) * 2005-03-18 2007-02-13 Agere Systems Inc. Driver circuit capable of providing rise and fall transitions that step smoothly in the transition regions
US20060253663A1 (en) * 2005-05-06 2006-11-09 Micron Technology, Inc. Memory device and method having a data bypass path to allow rapid testing and calibration
KR20070074312A (ko) * 2006-01-09 2007-07-12 삼성전자주식회사 출력 드라이버를 조절할 수 있는 반도체 메모리 장치
US7782091B2 (en) * 2006-11-14 2010-08-24 Aptina Imaging Corporation Apparatus, system, and method for driver circuits
CN102099993B (zh) * 2008-07-17 2014-10-29 亚德诺半导体股份有限公司 可控重叠驱动电路
KR100956781B1 (ko) * 2008-09-10 2010-05-12 주식회사 하이닉스반도체 데이터 출력회로
US9143121B2 (en) * 2012-08-29 2015-09-22 Qualcomm Incorporated System and method of adjusting a clock signal
US9164522B2 (en) * 2013-10-11 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Wake up bias circuit and method of using the same
JP6366436B2 (ja) 2014-09-10 2018-08-01 三菱電機株式会社 電圧制御装置
US10469075B2 (en) * 2017-05-31 2019-11-05 Silicon Laboratories Inc. Low-ringing output driver

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638187A (en) * 1985-10-01 1987-01-20 Vtc Incorporated CMOS output buffer providing high drive current with minimum output signal distortion
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
JPH02124632A (ja) 1988-07-19 1990-05-11 Nec Corp 出力バッファ回路
JP2766109B2 (ja) 1992-01-29 1998-06-18 九州日本電気株式会社 出力バッファ
GB9224685D0 (en) * 1992-11-25 1993-01-13 Inmos Ltd Controlled impedance transistor switch circuit
US5426376A (en) * 1993-04-23 1995-06-20 Vlsi Technology, Inc. Noise isolated I/O buffer that uses two separate power supplies
US5570294A (en) * 1994-03-11 1996-10-29 Advanced Micro Devices Circuit configuration employing a compare unit for testing variably controlled delay units
US5519344A (en) * 1994-06-30 1996-05-21 Proebsting; Robert J. Fast propagation technique in CMOS integrated circuits
JP3537500B2 (ja) * 1994-08-16 2004-06-14 バー−ブラウン・コーポレーション インバータ装置
US5548237A (en) * 1995-03-10 1996-08-20 International Business Machines Corporation Process tolerant delay circuit
GB2305082B (en) * 1995-09-06 1999-10-06 At & T Corp Wave shaping transmit circuit
JPH09162719A (ja) 1995-12-08 1997-06-20 Mitsubishi Electric Corp 出力バッファ
JPH10242834A (ja) * 1997-02-26 1998-09-11 Nippon Precision Circuits Kk Ｃｍｏｓ回路
US6087847A (en) * 1997-07-29 2000-07-11 Intel Corporation Impedance control circuit
US5969552A (en) * 1998-01-15 1999-10-19 Silicon Image, Inc. Dual loop delay-locked loop
US5963071A (en) * 1998-01-22 1999-10-05 Nanoamp Solutions, Inc. Frequency doubler with adjustable duty cycle
JPH11308087A (ja) * 1998-04-24 1999-11-05 Mitsubishi Electric Corp スルーレートコントロール付き出力バッファ回路
US6097231A (en) * 1998-05-29 2000-08-01 Ramtron International Corporation CMOS RC equivalent delay circuit

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