JP4101973B2 - 出力バッファ回路 - Google Patents

出力バッファ回路 Download PDF

Info

Publication number
JP4101973B2
JP4101973B2 JP14125099A JP14125099A JP4101973B2 JP 4101973 B2 JP4101973 B2 JP 4101973B2 JP 14125099 A JP14125099 A JP 14125099A JP 14125099 A JP14125099 A JP 14125099A JP 4101973 B2 JP4101973 B2 JP 4101973B2
Authority
JP
Japan
Prior art keywords
output
signal
delay
output buffer
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP14125099A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000332593A5 (https=
JP2000332593A (ja
Inventor
正浩 横山
浩司 那須
修一 白田
幸枝 黒田
照明 神崎
暁人 上原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP14125099A priority Critical patent/JP4101973B2/ja
Priority to US09/421,932 priority patent/US6586973B2/en
Publication of JP2000332593A publication Critical patent/JP2000332593A/ja
Publication of JP2000332593A5 publication Critical patent/JP2000332593A5/ja
Application granted granted Critical
Publication of JP4101973B2 publication Critical patent/JP4101973B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H03K17/167—Soft switching using parallel switching arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/159—Applications of delay lines not covered by the preceding subgroups

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
JP14125099A 1999-05-21 1999-05-21 出力バッファ回路 Expired - Fee Related JP4101973B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP14125099A JP4101973B2 (ja) 1999-05-21 1999-05-21 出力バッファ回路
US09/421,932 US6586973B2 (en) 1999-05-21 1999-10-21 Output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14125099A JP4101973B2 (ja) 1999-05-21 1999-05-21 出力バッファ回路

Publications (3)

Publication Number Publication Date
JP2000332593A JP2000332593A (ja) 2000-11-30
JP2000332593A5 JP2000332593A5 (https=) 2006-06-15
JP4101973B2 true JP4101973B2 (ja) 2008-06-18

Family

ID=15287575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14125099A Expired - Fee Related JP4101973B2 (ja) 1999-05-21 1999-05-21 出力バッファ回路

Country Status (2)

Country Link
US (1) US6586973B2 (https=)
JP (1) JP4101973B2 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3667690B2 (ja) 2001-12-19 2005-07-06 エルピーダメモリ株式会社 出力バッファ回路及び半導体集積回路装置
US7199616B2 (en) * 2004-11-29 2007-04-03 Exar Corporation Method and apparatus to generate break before make signals for high speed TTL driver
US7176743B2 (en) * 2005-03-18 2007-02-13 Agere Systems Inc. Driver circuit capable of providing rise and fall transitions that step smoothly in the transition regions
US20060253663A1 (en) * 2005-05-06 2006-11-09 Micron Technology, Inc. Memory device and method having a data bypass path to allow rapid testing and calibration
KR20070074312A (ko) * 2006-01-09 2007-07-12 삼성전자주식회사 출력 드라이버를 조절할 수 있는 반도체 메모리 장치
US7782091B2 (en) * 2006-11-14 2010-08-24 Aptina Imaging Corporation Apparatus, system, and method for driver circuits
CN102099993B (zh) * 2008-07-17 2014-10-29 亚德诺半导体股份有限公司 可控重叠驱动电路
KR100956781B1 (ko) * 2008-09-10 2010-05-12 주식회사 하이닉스반도체 데이터 출력회로
US9143121B2 (en) * 2012-08-29 2015-09-22 Qualcomm Incorporated System and method of adjusting a clock signal
US9164522B2 (en) * 2013-10-11 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Wake up bias circuit and method of using the same
JP6366436B2 (ja) 2014-09-10 2018-08-01 三菱電機株式会社 電圧制御装置
US10469075B2 (en) * 2017-05-31 2019-11-05 Silicon Laboratories Inc. Low-ringing output driver

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638187A (en) * 1985-10-01 1987-01-20 Vtc Incorporated CMOS output buffer providing high drive current with minimum output signal distortion
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
JPH02124632A (ja) 1988-07-19 1990-05-11 Nec Corp 出力バッファ回路
JP2766109B2 (ja) 1992-01-29 1998-06-18 九州日本電気株式会社 出力バッファ
GB9224685D0 (en) * 1992-11-25 1993-01-13 Inmos Ltd Controlled impedance transistor switch circuit
US5426376A (en) * 1993-04-23 1995-06-20 Vlsi Technology, Inc. Noise isolated I/O buffer that uses two separate power supplies
US5570294A (en) * 1994-03-11 1996-10-29 Advanced Micro Devices Circuit configuration employing a compare unit for testing variably controlled delay units
US5519344A (en) * 1994-06-30 1996-05-21 Proebsting; Robert J. Fast propagation technique in CMOS integrated circuits
JP3537500B2 (ja) * 1994-08-16 2004-06-14 バー−ブラウン・コーポレーション インバータ装置
US5548237A (en) * 1995-03-10 1996-08-20 International Business Machines Corporation Process tolerant delay circuit
GB2305082B (en) * 1995-09-06 1999-10-06 At & T Corp Wave shaping transmit circuit
JPH09162719A (ja) 1995-12-08 1997-06-20 Mitsubishi Electric Corp 出力バッファ
JPH10242834A (ja) * 1997-02-26 1998-09-11 Nippon Precision Circuits Kk Ｃｍｏｓ回路
US6087847A (en) * 1997-07-29 2000-07-11 Intel Corporation Impedance control circuit
US5969552A (en) * 1998-01-15 1999-10-19 Silicon Image, Inc. Dual loop delay-locked loop
US5963071A (en) * 1998-01-22 1999-10-05 Nanoamp Solutions, Inc. Frequency doubler with adjustable duty cycle
JPH11308087A (ja) * 1998-04-24 1999-11-05 Mitsubishi Electric Corp スルーレートコントロール付き出力バッファ回路
US6097231A (en) * 1998-05-29 2000-08-01 Ramtron International Corporation CMOS RC equivalent delay circuit

Also Published As

Publication number Publication date
US6586973B2 (en) 2003-07-01
US20020075049A1 (en) 2002-06-20
JP2000332593A (ja) 2000-11-30

Similar Documents

Publication Publication Date Title
JP4101973B2 (ja) 出力バッファ回路
US7765415B2 (en) Semiconductor integrated circuit
US7930575B2 (en) Microcontroller for controlling power shutdown process
JP4437541B2 (ja) リセット制御回路及びリセット制御方法
US8386988B2 (en) Semiconductor integrated circuit and operating voltage control method
TWI405408B (zh) 可連續提供電源之切換控制方法及其相關裝置與電源供應系統
JPH0720968A (ja) 電圧と周波数を動的に変更することによってコンピュータの消費電力を減少させる方法
TWI531163B (zh) 電壓轉換器
US20080218224A1 (en) Semiconductor integrated circuit
US7538581B2 (en) Fast AC coupled level translator
JP2001160042A (ja) 温度センサ搭載のマイクロコンピュータ
US6621328B2 (en) Semiconductor device
EP0510833A2 (en) Data processing apparatus having address decoder
CN101872997B (zh) 连续提供电源的切换控制方法及其装置与电源供应系统
US9075588B2 (en) Voltage regulator and control circuit for supplying voltage to a plurality of subcircuits via a chain of switches
US20110004745A1 (en) Method of Controlling a Measurement Instrument
WO2018009747A2 (en) Electronic power switch
JP4924701B2 (ja) リセット制御回路及びリセット制御方法
US5430387A (en) Transition-controlled off-chip driver
US6647500B1 (en) System and method to generate a float voltage potential at output when first and second power supplies fail to supply power at the same time
CN219436662U (zh) 电源监测电路、电源管理系统和存储主控芯片
US20120223756A1 (en) Method and System for High Speed, Low Power and Small Flip-Flops
CN104883169B (zh) 用于功率门控芯片器件中的硬件部件的方法和装置
US11996850B2 (en) Comparator with reduced offset
JP4953161B2 (ja) 電子装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060425

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060425

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071023

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071218

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080214

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080214

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080311

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080321

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110328

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110328

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110328

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110328

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120328

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130328

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130328

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140328

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees