JP2000215680A - メモリ制御回路 - Google Patents

メモリ制御回路

Info

Publication number
JP2000215680A
JP2000215680A JP1344999A JP1344999A JP2000215680A JP 2000215680 A JP2000215680 A JP 2000215680A JP 1344999 A JP1344999 A JP 1344999A JP 1344999 A JP1344999 A JP 1344999A JP 2000215680 A JP2000215680 A JP 2000215680A
Authority
JP
Japan
Prior art keywords
data
memory
control circuit
memory cell
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1344999A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000215680A5 (enExample
Inventor
Akira Hamakawa
彰 浜川
Kazuya Sugita
一也 杉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1344999A priority Critical patent/JP2000215680A/ja
Priority to US09/330,220 priority patent/US6075731A/en
Publication of JP2000215680A publication Critical patent/JP2000215680A/ja
Publication of JP2000215680A5 publication Critical patent/JP2000215680A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
JP1344999A 1999-01-21 1999-01-21 メモリ制御回路 Pending JP2000215680A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1344999A JP2000215680A (ja) 1999-01-21 1999-01-21 メモリ制御回路
US09/330,220 US6075731A (en) 1999-01-21 1999-06-11 Memory control apparatus having data retention capabilities

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1344999A JP2000215680A (ja) 1999-01-21 1999-01-21 メモリ制御回路

Publications (2)

Publication Number Publication Date
JP2000215680A true JP2000215680A (ja) 2000-08-04
JP2000215680A5 JP2000215680A5 (enExample) 2005-11-04

Family

ID=11833460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1344999A Pending JP2000215680A (ja) 1999-01-21 1999-01-21 メモリ制御回路

Country Status (2)

Country Link
US (1) US6075731A (enExample)
JP (1) JP2000215680A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011204065A (ja) * 2010-03-26 2011-10-13 Mitsubishi Electric Corp データ記憶装置
JP2012133875A (ja) * 2010-12-22 2012-07-12 Hitachi Global Storage Technologies Netherlands Bv テストセルを用いたフラッシュメモリの劣化の早期検出

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7211044B2 (en) * 2001-05-29 2007-05-01 Ethicon Endo-Surgery, Inc. Method for mapping temperature rise using pulse-echo ultrasound
JP3692418B2 (ja) * 2002-10-09 2005-09-07 沖電気工業株式会社 半導体装置の誤動作防止回路
US20090027942A1 (en) * 2004-04-26 2009-01-29 Applied Interllectual Properties Semiconductor memory unit and array
US20080123430A1 (en) * 2006-06-29 2008-05-29 Applied Intellectual Property Co., Ltd. Non-volatile memory unit and array
US7334182B2 (en) * 2004-11-24 2008-02-19 Northrop Grumman Corporation Serial data preservation method
JP5731730B2 (ja) * 2008-01-11 2015-06-10 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びその半導体記憶装置を含むデータ処理システム
CN109935252B (zh) * 2017-12-15 2021-03-30 旺宏电子股份有限公司 存储器装置及其操作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128097A (ja) * 1985-11-27 1987-06-10 Mitsubishi Electric Corp 不揮発生メモリ装置
US5276856A (en) * 1989-09-28 1994-01-04 Pixel Semiconductor, Inc. Memory controller flexible timing control system and method
JPH08297987A (ja) * 1995-04-26 1996-11-12 Toshiba Corp 不揮発性半導体記憶装置
JP3789542B2 (ja) * 1996-04-04 2006-06-28 富士通株式会社 メモリ制御回路
JPH09320300A (ja) * 1996-05-28 1997-12-12 Mitsubishi Electric Corp 半導体記憶装置
US5901103A (en) * 1997-04-07 1999-05-04 Motorola, Inc. Integrated circuit having standby control for memory and method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011204065A (ja) * 2010-03-26 2011-10-13 Mitsubishi Electric Corp データ記憶装置
JP2012133875A (ja) * 2010-12-22 2012-07-12 Hitachi Global Storage Technologies Netherlands Bv テストセルを用いたフラッシュメモリの劣化の早期検出

Also Published As

Publication number Publication date
US6075731A (en) 2000-06-13

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