ITMI920120A0 - Disposizione di una schiera di celle ridondanti per un dispositivo di memoria a semiconduttore - Google Patents

Disposizione di una schiera di celle ridondanti per un dispositivo di memoria a semiconduttore

Info

Publication number
ITMI920120A0
ITMI920120A0 IT92MI120A ITMI920120A ITMI920120A0 IT MI920120 A0 ITMI920120 A0 IT MI920120A0 IT 92MI120 A IT92MI120 A IT 92MI120A IT MI920120 A ITMI920120 A IT MI920120A IT MI920120 A0 ITMI920120 A0 IT MI920120A0
Authority
IT
Italy
Prior art keywords
arrangement
memory device
semiconductor memory
redundant cell
cell arrangement
Prior art date
Application number
IT92MI120A
Other languages
English (en)
Inventor
Tae-Jin Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI920120A0 publication Critical patent/ITMI920120A0/it
Publication of ITMI920120A1 publication Critical patent/ITMI920120A1/it
Application granted granted Critical
Publication of IT1258816B publication Critical patent/IT1258816B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
ITMI920120A 1991-08-21 1992-01-23 Disposizione di una schiera di celle ridondanti per un dispositivo di memoria a semiconduttore IT1258816B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910014407A KR940008211B1 (ko) 1991-08-21 1991-08-21 반도체메모리장치의 리던던트 셀 어레이 배열방법

Publications (3)

Publication Number Publication Date
ITMI920120A0 true ITMI920120A0 (it) 1992-01-23
ITMI920120A1 ITMI920120A1 (it) 1993-07-23
IT1258816B IT1258816B (it) 1996-02-29

Family

ID=19318849

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI920120A IT1258816B (it) 1991-08-21 1992-01-23 Disposizione di una schiera di celle ridondanti per un dispositivo di memoria a semiconduttore

Country Status (7)

Country Link
US (1) US5355337A (it)
JP (1) JPH0562497A (it)
KR (1) KR940008211B1 (it)
DE (1) DE4201847C2 (it)
FR (1) FR2680590B1 (it)
GB (1) GB2258931B (it)
IT (1) IT1258816B (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06338199A (ja) * 1993-05-27 1994-12-06 Hitachi Ltd 半導体記憶装置
US5440517A (en) * 1994-08-15 1995-08-08 Micron Technology, Inc. DRAMs having on-chip row copy circuits for use in testing and video imaging and method for operating same
KR0174338B1 (ko) * 1994-11-30 1999-04-01 윌리엄 티. 엘리스 간단하게 테스트할 수 있는 구성을 갖는 랜덤 액세스 메모리
US5544113A (en) * 1994-11-30 1996-08-06 International Business Machines Corporation Random access memory having a flexible array redundancy scheme
DE69727059D1 (de) * 1997-10-20 2004-02-05 St Microelectronics Srl CAD für redundante Speichervorrichtungen
DE69909969D1 (de) * 1999-05-12 2003-09-04 St Microelectronics Srl Unflüchtiger Speicher mit Zeilenredundanz
JP2005338926A (ja) 2004-05-24 2005-12-08 Toshiba Corp 携帯可能電子装置
US7676776B2 (en) * 2007-06-25 2010-03-09 International Business Machines Corporation Spare gate array cell distribution analysis
KR102412610B1 (ko) 2015-12-24 2022-06-23 삼성전자주식회사 포스트 패키지 리페어 동작을 수행하는 메모리 장치

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4281398A (en) * 1980-02-12 1981-07-28 Mostek Corporation Block redundancy for memory array
US4796233A (en) * 1984-10-19 1989-01-03 Fujitsu Limited Bipolar-transistor type semiconductor memory device having redundancy configuration
US4745582A (en) * 1984-10-19 1988-05-17 Fujitsu Limited Bipolar-transistor type random access memory device having redundancy configuration
US4829481A (en) * 1985-08-20 1989-05-09 Sgs-Thomson Microelectronics, Inc. Defective element disabling circuit having a laser-blown fuse
JP2530610B2 (ja) * 1986-02-27 1996-09-04 富士通株式会社 半導体記憶装置
KR890003691B1 (ko) * 1986-08-22 1989-09-30 삼성전자 주식회사 블럭 열 리던던씨 회로
JPS63168900A (ja) * 1987-01-06 1988-07-12 Toshiba Corp 半導体記憶装置
JP2558787B2 (ja) * 1988-02-15 1996-11-27 松下電子工業株式会社 記憶装置
US4866676A (en) * 1988-03-24 1989-09-12 Motorola, Inc. Testing arrangement for a DRAM with redundancy
JPH0235699A (ja) * 1988-07-26 1990-02-06 Nec Corp 化合物半導体メモリデバイス
JP2999477B2 (ja) * 1989-01-19 2000-01-17 三菱電機株式会社 半導体記憶装置
KR910005601B1 (ko) * 1989-05-24 1991-07-31 삼성전자주식회사 리던던트 블럭을 가지는 반도체 메모리장치
JPH02310898A (ja) * 1989-05-25 1990-12-26 Nec Corp メモリ回路
EP0411626B1 (en) * 1989-08-04 1995-10-25 Fujitsu Limited Semiconductor memory device having a redundancy

Also Published As

Publication number Publication date
GB2258931A (en) 1993-02-24
FR2680590B1 (fr) 1994-12-09
FR2680590A1 (fr) 1993-02-26
DE4201847A1 (de) 1993-02-25
GB9201272D0 (en) 1992-03-11
DE4201847C2 (de) 1994-02-17
IT1258816B (it) 1996-02-29
KR930005036A (ko) 1993-03-23
US5355337A (en) 1994-10-11
JPH0562497A (ja) 1993-03-12
KR940008211B1 (ko) 1994-09-08
ITMI920120A1 (it) 1993-07-23
GB2258931B (en) 1995-06-14

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960830