ITMI913179A1 - Circuito di trasmissione di dati con linee di ingresso/uscita segmentate - Google Patents
Circuito di trasmissione di dati con linee di ingresso/uscita segmentateInfo
- Publication number
- ITMI913179A1 ITMI913179A1 IT003179A ITMI913179A ITMI913179A1 IT MI913179 A1 ITMI913179 A1 IT MI913179A1 IT 003179 A IT003179 A IT 003179A IT MI913179 A ITMI913179 A IT MI913179A IT MI913179 A1 ITMI913179 A1 IT MI913179A1
- Authority
- IT
- Italy
- Prior art keywords
- data transmission
- transmission circuit
- output lines
- segmented input
- segmented
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910012632A KR940007639B1 (ko) | 1991-07-23 | 1991-07-23 | 분할된 입출력 라인을 갖는 데이타 전송회로 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI913179A0 ITMI913179A0 (it) | 1991-11-28 |
ITMI913179A1 true ITMI913179A1 (it) | 1993-05-28 |
IT1252336B IT1252336B (it) | 1995-06-08 |
Family
ID=19317690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI913179A IT1252336B (it) | 1991-07-23 | 1991-11-28 | Circuito di trasmissione di dati con linee di ingresso/uscita segmentate |
Country Status (7)
Country | Link |
---|---|
US (1) | US5274595A (it) |
JP (1) | JP2562856B2 (it) |
KR (1) | KR940007639B1 (it) |
DE (1) | DE4138312C2 (it) |
FR (1) | FR2679672B1 (it) |
GB (1) | GB2258071B (it) |
IT (1) | IT1252336B (it) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR940007640B1 (ko) * | 1991-07-31 | 1994-08-22 | 삼성전자 주식회사 | 공통 입출력선을 가지는 데이타 전송회로 |
JP2775552B2 (ja) * | 1991-12-26 | 1998-07-16 | 三菱電機株式会社 | 半導体記憶装置 |
EP0579862A1 (de) * | 1992-07-24 | 1994-01-26 | Siemens Aktiengesellschaft | Integrierte Halbleiterspeicheranordnung |
JP2663838B2 (ja) * | 1993-07-27 | 1997-10-15 | 日本電気株式会社 | 半導体集積回路装置 |
JP3305449B2 (ja) * | 1993-09-17 | 2002-07-22 | 富士通株式会社 | 半導体記憶装置 |
JP3048498B2 (ja) * | 1994-04-13 | 2000-06-05 | 株式会社東芝 | 半導体記憶装置 |
JP3666671B2 (ja) * | 1994-12-20 | 2005-06-29 | 株式会社日立製作所 | 半導体装置 |
KR100370952B1 (ko) * | 1995-12-31 | 2003-03-28 | 주식회사 하이닉스반도체 | 메모리 셀의 센스앰프 회로 |
JP2000100172A (ja) | 1998-07-22 | 2000-04-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2000243086A (ja) * | 1998-12-24 | 2000-09-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6137746A (en) * | 1999-07-28 | 2000-10-24 | Alliance Semiconductor Corporation | High performance random access memory with multiple local I/O lines |
JP4667594B2 (ja) * | 2000-12-25 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
KR100555568B1 (ko) * | 2004-08-03 | 2006-03-03 | 삼성전자주식회사 | 온/오프 제어가 가능한 로컬 센스 증폭 회로를 구비하는반도체 메모리 장치 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5683891A (en) * | 1979-12-13 | 1981-07-08 | Fujitsu Ltd | Semiconductor storage device |
JPS58125291A (ja) * | 1982-01-20 | 1983-07-26 | Hitachi Ltd | Mosスタテイツク型ram |
JPS5948889A (ja) * | 1982-09-10 | 1984-03-21 | Hitachi Ltd | Mos記憶装置 |
JPS60119698A (ja) * | 1983-12-01 | 1985-06-27 | Fujitsu Ltd | 半導体メモリ |
JPS6074197A (ja) * | 1984-04-27 | 1985-04-26 | Nec Corp | メモリ回路 |
JPS62167698A (ja) * | 1986-01-20 | 1987-07-24 | Fujitsu Ltd | 半導体記億装置 |
JPH07111823B2 (ja) * | 1986-03-18 | 1995-11-29 | 三菱電機株式会社 | 半導体記憶装置 |
JPS62231495A (ja) * | 1986-03-31 | 1987-10-12 | Toshiba Corp | 半導体記憶装置 |
US4807194A (en) * | 1986-04-24 | 1989-02-21 | Matsushita Electric Industrial Co., Ltd. | Seimiconductor memory device having sub bit lines |
JPS63161596A (ja) * | 1986-12-25 | 1988-07-05 | Nec Corp | 半導体記憶装置 |
JPS63200391A (ja) * | 1987-02-16 | 1988-08-18 | Toshiba Corp | スタテイツク型半導体メモリ |
JPH01171195A (ja) * | 1987-12-25 | 1989-07-06 | Sony Corp | メモリ装置 |
US4947059A (en) * | 1988-05-19 | 1990-08-07 | Samsung Electronics Co. Ltd. | Method of dividing an input-output line by decoding |
JP2509306B2 (ja) * | 1988-08-16 | 1996-06-19 | 沖電気工業株式会社 | 半導体記憶装置 |
KR910009444B1 (ko) * | 1988-12-20 | 1991-11-16 | 삼성전자 주식회사 | 반도체 메모리 장치 |
JP2809676B2 (ja) * | 1989-03-23 | 1998-10-15 | 株式会社東芝 | ダイナミック型半導体メモリ装置 |
US5023837A (en) * | 1989-09-05 | 1991-06-11 | Texas Instruments Incorporated | Bitline segmentation in logic arrays |
JP3101297B2 (ja) * | 1990-03-30 | 2000-10-23 | 株式会社東芝 | 半導体メモリ装置 |
JP3101298B2 (ja) * | 1990-03-30 | 2000-10-23 | 株式会社東芝 | 半導体メモリ装置 |
DE69127918T2 (de) * | 1990-03-30 | 1998-04-02 | Fujitsu Ltd | Signalverstärkerschaltung und Halbleiterspeicher diese verwendend |
-
1991
- 1991-07-23 KR KR1019910012632A patent/KR940007639B1/ko not_active IP Right Cessation
- 1991-10-16 US US07/777,133 patent/US5274595A/en not_active Expired - Lifetime
- 1991-10-30 FR FR9113381A patent/FR2679672B1/fr not_active Expired - Fee Related
- 1991-11-21 DE DE4138312A patent/DE4138312C2/de not_active Expired - Fee Related
- 1991-11-25 GB GB9124992A patent/GB2258071B/en not_active Expired - Fee Related
- 1991-11-28 IT ITMI913179A patent/IT1252336B/it active IP Right Grant
- 1991-11-29 JP JP3339469A patent/JP2562856B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2258071A (en) | 1993-01-27 |
FR2679672B1 (fr) | 1994-04-15 |
IT1252336B (it) | 1995-06-08 |
KR930003143A (ko) | 1993-02-24 |
JPH0528767A (ja) | 1993-02-05 |
JP2562856B2 (ja) | 1996-12-11 |
KR940007639B1 (ko) | 1994-08-22 |
FR2679672A1 (fr) | 1993-01-29 |
US5274595A (en) | 1993-12-28 |
DE4138312C2 (de) | 1995-10-26 |
DE4138312A1 (de) | 1993-01-28 |
GB9124992D0 (en) | 1992-01-22 |
ITMI913179A0 (it) | 1991-11-28 |
GB2258071B (en) | 1995-01-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19971126 |