IT8806622A0 - Processo di saldatura di fette di silicio fra loro, per la fabbricazione di dispositivi a semiconduttore - Google Patents

Processo di saldatura di fette di silicio fra loro, per la fabbricazione di dispositivi a semiconduttore

Info

Publication number
IT8806622A0
IT8806622A0 IT8806622A IT662288A IT8806622A0 IT 8806622 A0 IT8806622 A0 IT 8806622A0 IT 8806622 A IT8806622 A IT 8806622A IT 662288 A IT662288 A IT 662288A IT 8806622 A0 IT8806622 A0 IT 8806622A0
Authority
IT
Italy
Prior art keywords
manufacture
semiconductor devices
silicon wafers
wafers together
soldering silicon
Prior art date
Application number
IT8806622A
Other languages
English (en)
Other versions
IT1230026B (it
Inventor
Ronsisvalle Cesare
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8806622A priority Critical patent/IT1230026B/it
Publication of IT8806622A0 publication Critical patent/IT8806622A0/it
Priority to EP19890202692 priority patent/EP0366208A3/en
Priority to JP1278779A priority patent/JPH02170514A/ja
Application granted granted Critical
Publication of IT1230026B publication Critical patent/IT1230026B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
IT8806622A 1988-10-28 1988-10-28 Processo di saldatura di fette di silicio fra loro, per la fabbricazione di dispositivi a semiconduttore IT1230026B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT8806622A IT1230026B (it) 1988-10-28 1988-10-28 Processo di saldatura di fette di silicio fra loro, per la fabbricazione di dispositivi a semiconduttore
EP19890202692 EP0366208A3 (en) 1988-10-28 1989-10-26 Method for bonding silicon wafers together, for manufacturing semiconductor devices
JP1278779A JPH02170514A (ja) 1988-10-28 1989-10-27 半導体装置製造のためのシリコンウェーハ相互接着方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8806622A IT1230026B (it) 1988-10-28 1988-10-28 Processo di saldatura di fette di silicio fra loro, per la fabbricazione di dispositivi a semiconduttore

Publications (2)

Publication Number Publication Date
IT8806622A0 true IT8806622A0 (it) 1988-10-28
IT1230026B IT1230026B (it) 1991-09-24

Family

ID=11121548

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8806622A IT1230026B (it) 1988-10-28 1988-10-28 Processo di saldatura di fette di silicio fra loro, per la fabbricazione di dispositivi a semiconduttore

Country Status (3)

Country Link
EP (1) EP0366208A3 (it)
JP (1) JPH02170514A (it)
IT (1) IT1230026B (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4036222A1 (de) * 1990-11-14 1992-05-21 Bosch Gmbh Robert Verfahren zur herstellung von halbleiterelementen, insbesondere von dioden
US5503704A (en) * 1993-01-06 1996-04-02 The Regents Of The University Of California Nitrogen based low temperature direct bonding
FR2935536B1 (fr) 2008-09-02 2010-09-24 Soitec Silicon On Insulator Procede de detourage progressif
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2961630B1 (fr) 2010-06-22 2013-03-29 Soitec Silicon On Insulator Technologies Appareil de fabrication de dispositifs semi-conducteurs
US8338266B2 (en) 2010-08-11 2012-12-25 Soitec Method for molecular adhesion bonding at low pressure
FR2964193A1 (fr) 2010-08-24 2012-03-02 Soitec Silicon On Insulator Procede de mesure d'une energie d'adhesion, et substrats associes

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770475B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 半導体基板の製造方法
JPS61182216A (ja) * 1985-02-08 1986-08-14 Toshiba Corp 半導体基板の接合方法
JPH0783050B2 (ja) * 1985-06-21 1995-09-06 株式会社東芝 半導体素子の製造方法
JP2633536B2 (ja) * 1986-11-05 1997-07-23 株式会社東芝 接合型半導体基板の製造方法

Also Published As

Publication number Publication date
EP0366208A2 (en) 1990-05-02
IT1230026B (it) 1991-09-24
EP0366208A3 (en) 1991-03-06
JPH02170514A (ja) 1990-07-02

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