IT8319237A0 - Procedimento per la fabbricazione di dispositivi a circuiti integrati a semiconduttori. - Google Patents

Procedimento per la fabbricazione di dispositivi a circuiti integrati a semiconduttori.

Info

Publication number
IT8319237A0
IT8319237A0 IT8319237A IT1923783A IT8319237A0 IT 8319237 A0 IT8319237 A0 IT 8319237A0 IT 8319237 A IT8319237 A IT 8319237A IT 1923783 A IT1923783 A IT 1923783A IT 8319237 A0 IT8319237 A0 IT 8319237A0
Authority
IT
Italy
Prior art keywords
procedure
manufacture
integrated circuit
semiconductor integrated
circuit devices
Prior art date
Application number
IT8319237A
Other languages
English (en)
Other versions
IT1160471B (it
Inventor
Shigeo Kuroda
Takahiko Takahashi
Akio Anzai
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of IT8319237A0 publication Critical patent/IT8319237A0/it
Application granted granted Critical
Publication of IT1160471B publication Critical patent/IT1160471B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
IT19237/83A 1982-01-25 1983-01-21 Procedimento per la fabbricazione di dispositivi a circuiti integrati a semiconduttori IT1160471B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57008934A JPS58127374A (ja) 1982-01-25 1982-01-25 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
IT8319237A0 true IT8319237A0 (it) 1983-01-21
IT1160471B IT1160471B (it) 1987-03-11

Family

ID=11706491

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19237/83A IT1160471B (it) 1982-01-25 1983-01-21 Procedimento per la fabbricazione di dispositivi a circuiti integrati a semiconduttori

Country Status (7)

Country Link
US (1) US4469535A (it)
JP (1) JPS58127374A (it)
DE (1) DE3302352A1 (it)
GB (1) GB2117969B (it)
HK (1) HK46486A (it)
IT (1) IT1160471B (it)
MY (1) MY8600563A (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63205959A (ja) * 1987-02-21 1988-08-25 Matsushita Electric Works Ltd 静電誘導形半導体装置の製法
JPH01243529A (ja) * 1988-03-25 1989-09-28 Hitachi Ltd 半導体集積回路装置
JPH0516305U (ja) * 1991-08-27 1993-03-02 株式会社小森コーポレーシヨン 刷版加工機

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3992232A (en) * 1973-08-06 1976-11-16 Hitachi, Ltd. Method of manufacturing semiconductor device having oxide isolation structure and guard ring
GB1457139A (en) * 1973-09-27 1976-12-01 Hitachi Ltd Method of manufacturing semiconductor device
US3928081A (en) * 1973-10-26 1975-12-23 Signetics Corp Method for fabricating semiconductor devices using composite mask and ion implantation
GB1492447A (en) * 1974-07-25 1977-11-16 Siemens Ag Semiconductor devices
JPS5275989A (en) * 1975-12-22 1977-06-25 Hitachi Ltd Production of semiconductor device
FR2358748A1 (fr) * 1976-07-15 1978-02-10 Radiotechnique Compelec Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede
US4201800A (en) * 1978-04-28 1980-05-06 International Business Machines Corp. Hardened photoresist master image mask process
JPS5586151A (en) * 1978-12-23 1980-06-28 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor integrated circuit
FR2454698A1 (fr) * 1979-04-20 1980-11-14 Radiotechnique Compelec Procede de realisation de circuits integres a l'aide d'un masque multicouche et dispositifs obtenus par ce procede
JPS6028135B2 (ja) * 1979-05-18 1985-07-03 富士通株式会社 半導体装置の製造方法
US4376664A (en) * 1979-05-31 1983-03-15 Fujitsu Limited Method of producing a semiconductor device
DE3071380D1 (en) * 1979-05-31 1986-03-13 Fujitsu Ltd Method of producing a semiconductor device
CA1167981A (en) * 1980-12-23 1984-05-22 Gte Laboratories Incorporated Low capacitance self-aligned semiconductor electrode structure and method of fabrication
FR2498095A1 (fr) * 1981-01-20 1982-07-23 Vallourec Procede de fabrication d'ebauches d'essieux creux en une seule piece et ebauches d'essieux obtenues

Also Published As

Publication number Publication date
GB8301288D0 (en) 1983-02-16
MY8600563A (en) 1986-12-31
GB2117969A (en) 1983-10-19
JPS58127374A (ja) 1983-07-29
DE3302352A1 (de) 1983-09-08
GB2117969B (en) 1985-07-10
HK46486A (en) 1986-06-27
IT1160471B (it) 1987-03-11
US4469535A (en) 1984-09-04

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19940121