IT1167659B - Procedimento per la fabbricazione di un dispositivo a semiconduttori - Google Patents

Procedimento per la fabbricazione di un dispositivo a semiconduttori

Info

Publication number
IT1167659B
IT1167659B IT22981/83A IT2298183A IT1167659B IT 1167659 B IT1167659 B IT 1167659B IT 22981/83 A IT22981/83 A IT 22981/83A IT 2298183 A IT2298183 A IT 2298183A IT 1167659 B IT1167659 B IT 1167659B
Authority
IT
Italy
Prior art keywords
procedure
manufacture
semiconductor device
semiconductor
Prior art date
Application number
IT22981/83A
Other languages
English (en)
Other versions
IT8322981A0 (it
Inventor
Nagasawa Kouichi
Ikeda Shuji
Suzuki Norio
Sakai Yoshio
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of IT8322981A0 publication Critical patent/IT8322981A0/it
Application granted granted Critical
Publication of IT1167659B publication Critical patent/IT1167659B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT22981/83A 1982-09-24 1983-09-23 Procedimento per la fabbricazione di un dispositivo a semiconduttori IT1167659B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57164832A JPS5955054A (ja) 1982-09-24 1982-09-24 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
IT8322981A0 IT8322981A0 (it) 1983-09-23
IT1167659B true IT1167659B (it) 1987-05-13

Family

ID=15800773

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22981/83A IT1167659B (it) 1982-09-24 1983-09-23 Procedimento per la fabbricazione di un dispositivo a semiconduttori

Country Status (10)

Country Link
US (1) US4549340A (it)
JP (1) JPS5955054A (it)
KR (1) KR910006674B1 (it)
DE (1) DE3334153A1 (it)
FR (1) FR2533749B1 (it)
GB (1) GB2128401B (it)
HK (1) HK71187A (it)
IT (1) IT1167659B (it)
MY (1) MY8700604A (it)
SG (1) SG37487G (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116167A (ja) * 1983-11-29 1985-06-22 Toshiba Corp 半導体記憶装置及びその製造方法
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4642878A (en) * 1984-08-28 1987-02-17 Kabushiki Kaisha Toshiba Method of making MOS device by sequentially depositing an oxidizable layer and a masking second layer over gated device regions
KR940006668B1 (ko) * 1984-11-22 1994-07-25 가부시끼가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치의 제조방법
DE3572086D1 (en) * 1984-12-13 1989-09-07 Siemens Ag Method of producing an isolation separating the active regions of a highly integrated cmos circuit
US4675982A (en) * 1985-10-31 1987-06-30 International Business Machines Corporation Method of making self-aligned recessed oxide isolation regions
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
JPH01151268A (ja) * 1987-12-08 1989-06-14 Mitsubishi Electric Corp 半導体装置の製造方法
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
JPH03155661A (ja) * 1989-08-02 1991-07-03 Nec Corp Ｃｍｏｓトランジスタのｎウェルの製造方法
GB2237445B (en) * 1989-10-04 1994-01-12 Seagate Microelectron Ltd A semiconductor device fabrication process
EP0511877A1 (en) * 1991-05-01 1992-11-04 STMicroelectronics, Inc. Manufacture of CMOS devices
US5204279A (en) * 1991-06-03 1993-04-20 Sgs-Thomson Microelectronics, Inc. Method of making SRAM cell and structure with polycrystalline p-channel load devices
US5187114A (en) * 1991-06-03 1993-02-16 Sgs-Thomson Microelectronics, Inc. Method of making SRAM cell and structure with polycrystalline P-channel load devices
US5525823A (en) * 1992-05-08 1996-06-11 Sgs-Thomson Microelectronics, Inc. Manufacture of CMOS devices
US5292681A (en) * 1993-09-16 1994-03-08 Micron Semiconductor, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
US5731218A (en) * 1993-11-02 1998-03-24 Siemens Aktiengesellschaft Method for producing a contact hole to a doped region
JP2934738B2 (ja) 1994-03-18 1999-08-16 セイコーインスツルメンツ株式会社 半導体装置およびその製造方法
JPH09260510A (ja) * 1996-01-17 1997-10-03 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH11330385A (ja) 1998-05-20 1999-11-30 Mitsumi Electric Co Ltd Ｃｍｏｓデバイス
JP3890254B2 (ja) * 2002-05-07 2007-03-07 沖電気工業株式会社 半導体装置の製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1569872A (it) * 1968-04-10 1969-06-06
DE2127569A1 (de) * 1970-06-25 1971-12-30 Western Electric Co Verfahren zur Herstellung einer dicken Oxidausbildung auf integrierten Halbleiterschaltungen
US3865654A (en) * 1972-11-01 1975-02-11 Ibm Complementary field effect transistor having p doped silicon gates and process for making the same
US3821781A (en) * 1972-11-01 1974-06-28 Ibm Complementary field effect transistors having p doped silicon gates
CA1017073A (en) * 1974-06-03 1977-09-06 Fairchild Camera And Instrument Corporation Complementary insulated gate field effect transistor structure and process for fabricating the structure
US4208781A (en) * 1976-09-27 1980-06-24 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
JPS583380B2 (ja) * 1977-03-04 1983-01-21 株式会社日立製作所 半導体装置とその製造方法
JPS53115173A (en) * 1977-03-18 1978-10-07 Hitachi Ltd Production of semiconductor device
JPS5413779A (en) * 1977-07-04 1979-02-01 Toshiba Corp Semiconductor integrated circuit device
JPS5513953A (en) * 1978-07-18 1980-01-31 Fujitsu Ltd Complementary integrated circuit
JPS56124270A (en) * 1980-03-05 1981-09-29 Hitachi Ltd Manufacture of semiconductor device
JPS56150853A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Manufacture of semiconductor device
US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
NL187328C (nl) * 1980-12-23 1991-08-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
US4385947A (en) * 1981-07-29 1983-05-31 Harris Corporation Method for fabricating CMOS in P substrate with single guard ring using local oxidation
DE3133841A1 (de) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4420344A (en) * 1981-10-15 1983-12-13 Texas Instruments Incorporated CMOS Source/drain implant process without compensation of polysilicon doping
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
DE3149185A1 (de) * 1981-12-11 1983-06-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4435895A (en) * 1982-04-05 1984-03-13 Bell Telephone Laboratories, Incorporated Process for forming complementary integrated circuit devices
US4409726A (en) * 1982-04-08 1983-10-18 Philip Shiota Method of making well regions for CMOS devices

Also Published As

Publication number Publication date
GB2128401A (en) 1984-04-26
HK71187A (en) 1987-10-09
IT8322981A0 (it) 1983-09-23
MY8700604A (en) 1987-12-31
JPS5955054A (ja) 1984-03-29
GB8325513D0 (en) 1983-10-26
KR910006674B1 (ko) 1991-08-30
DE3334153A1 (de) 1984-03-29
FR2533749A1 (fr) 1984-03-30
GB2128401B (en) 1986-02-26
US4549340A (en) 1985-10-29
SG37487G (en) 1987-07-24
FR2533749B1 (fr) 1986-03-28
KR840005928A (ko) 1984-11-19

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