IT1168294B - Procedimento per fabbricare un dispositivo a circuito integrato a semiconduttori - Google Patents

Procedimento per fabbricare un dispositivo a circuito integrato a semiconduttori

Info

Publication number
IT1168294B
IT1168294B IT22983/83A IT2298383A IT1168294B IT 1168294 B IT1168294 B IT 1168294B IT 22983/83 A IT22983/83 A IT 22983/83A IT 2298383 A IT2298383 A IT 2298383A IT 1168294 B IT1168294 B IT 1168294B
Authority
IT
Italy
Prior art keywords
procedure
manufacturing
integrated circuit
semiconductor integrated
circuit device
Prior art date
Application number
IT22983/83A
Other languages
English (en)
Other versions
IT8322983A0 (it
Inventor
Anzai Norio
Yasuoka Hideki
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of IT8322983A0 publication Critical patent/IT8322983A0/it
Application granted granted Critical
Publication of IT1168294B publication Critical patent/IT1168294B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
IT22983/83A 1982-09-24 1983-09-23 Procedimento per fabbricare un dispositivo a circuito integrato a semiconduttori IT1168294B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57164840A JPS5955052A (ja) 1982-09-24 1982-09-24 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
IT8322983A0 IT8322983A0 (it) 1983-09-23
IT1168294B true IT1168294B (it) 1987-05-20

Family

ID=15800917

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22983/83A IT1168294B (it) 1982-09-24 1983-09-23 Procedimento per fabbricare un dispositivo a circuito integrato a semiconduttori

Country Status (10)

Country Link
US (1) US4529456A (it)
JP (1) JPS5955052A (it)
KR (1) KR920001403B1 (it)
DE (1) DE3334337A1 (it)
FR (1) FR2533751B1 (it)
GB (1) GB2128024B (it)
HK (1) HK71087A (it)
IT (1) IT1168294B (it)
MY (1) MY8700610A (it)
SG (1) SG36887G (it)

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JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法
US4637125A (en) * 1983-09-22 1987-01-20 Kabushiki Kaisha Toshiba Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor
US4536945A (en) * 1983-11-02 1985-08-27 National Semiconductor Corporation Process for producing CMOS structures with Schottky bipolar transistors
DE3402653A1 (de) * 1984-01-26 1985-08-01 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung speziell dotierter bereiche in halbleitermaterial
JPS60217657A (ja) * 1984-04-12 1985-10-31 Mitsubishi Electric Corp 半導体集積回路装置の製造方法
ATE59917T1 (de) * 1985-09-13 1991-01-15 Siemens Ag Integrierte bipolar- und komplementaere mostransistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung.
US6740958B2 (en) * 1985-09-25 2004-05-25 Renesas Technology Corp. Semiconductor memory device
US4797372A (en) * 1985-11-01 1989-01-10 Texas Instruments Incorporated Method of making a merge bipolar and complementary metal oxide semiconductor transistor device
US4963951A (en) * 1985-11-29 1990-10-16 General Electric Company Lateral insulated gate bipolar transistors with improved latch-up immunity
EP0248988B1 (de) * 1986-06-10 1990-10-31 Siemens Aktiengesellschaft Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen
JPH0797610B2 (ja) * 1986-06-18 1995-10-18 松下電子工業株式会社 Ｂｉ−ＣＭＯＳ集積回路
JPH0797609B2 (ja) * 1986-06-18 1995-10-18 松下電子工業株式会社 相補型ｍｉｓ集積回路
DE3787407D1 (de) * 1986-07-04 1993-10-21 Siemens Ag Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung.
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
JP2635961B2 (ja) * 1986-09-26 1997-07-30 株式会社日立製作所 半導体装置の製造方法
US5023690A (en) * 1986-10-24 1991-06-11 Texas Instruments Incorporated Merged bipolar and complementary metal oxide semiconductor transistor device
JPS6410644A (en) * 1987-07-02 1989-01-13 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS6437860A (en) * 1987-08-03 1989-02-08 Fujitsu Ltd Manufacture of bi-cmos semiconductor device
US5132235A (en) * 1987-08-07 1992-07-21 Siliconix Incorporated Method for fabricating a high voltage MOS transistor
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US5011784A (en) * 1988-01-21 1991-04-30 Exar Corporation Method of making a complementary BiCMOS process with isolated vertical PNP transistors
US5075241A (en) * 1988-01-29 1991-12-24 Texas Instruments Incorporated Method of forming a recessed contact bipolar transistor and field effect device
US5293077A (en) * 1988-02-29 1994-03-08 Hitachi, Ltd. Power switching circuit
EP0405045B1 (en) * 1989-06-28 1995-12-13 STMicroelectronics S.r.l. A mixed technology integrated circuit comprising CMOS structures and efficient lateral bipolar transistors with a high early voltage and fabrication thereof
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
US5013671A (en) * 1990-06-20 1991-05-07 Texas Instruments Incorporated Process for reduced emitter-base capacitance in bipolar transistor
US5124271A (en) * 1990-06-20 1992-06-23 Texas Instruments Incorporated Process for fabricating a BiCMOS integrated circuit
GB9112783D0 (en) * 1991-06-13 1991-07-31 Cmb Foodcan Plc Can ends
US5248624A (en) * 1991-08-23 1993-09-28 Exar Corporation Method of making isolated vertical pnp transistor in a complementary bicmos process with eeprom memory
US5422508A (en) * 1992-09-21 1995-06-06 Siliconix Incorporated BiCDMOS structure
US5648281A (en) * 1992-09-21 1997-07-15 Siliconix Incorporated Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate
US5698884A (en) * 1996-02-07 1997-12-16 Thunderbird Technologies, Inc. Short channel fermi-threshold field effect transistors including drain field termination region and methods of fabricating same
US5843814A (en) * 1996-02-15 1998-12-01 Micron Technology, Inc. Method of forming BiCMOS circuitry
US6133123A (en) 1997-08-21 2000-10-17 Micron Technology, Inc. Fabrication of semiconductor gettering structures by ion implantation
KR100350648B1 (ko) * 2000-01-17 2002-08-28 페어차일드코리아반도체 주식회사 모스 트랜지스터 및 그 제조 방법
US6528850B1 (en) * 2000-05-03 2003-03-04 Linear Technology Corporation High voltage MOS transistor with up-retro well
JP2003017603A (ja) 2001-06-28 2003-01-17 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100456691B1 (ko) * 2002-03-05 2004-11-10 삼성전자주식회사 이중격리구조를 갖는 반도체 소자 및 그 제조방법
JP5684450B2 (ja) * 2008-08-20 2015-03-11 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
JP2012114401A (ja) * 2010-11-05 2012-06-14 Sharp Corp 半導体装置およびその製造方法
US9793153B2 (en) * 2011-09-20 2017-10-17 Alpha And Omega Semiconductor Incorporated Low cost and mask reduction method for high voltage devices

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JPS5851561A (ja) * 1981-09-24 1983-03-26 Hitachi Ltd 半導体集積回路装置
JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法

Also Published As

Publication number Publication date
DE3334337A1 (de) 1984-03-29
GB2128024B (en) 1986-01-02
GB8324163D0 (en) 1983-10-12
KR920001403B1 (ko) 1992-02-13
KR840005926A (ko) 1984-11-19
GB2128024A (en) 1984-04-18
SG36887G (en) 1987-09-18
JPS5955052A (ja) 1984-03-29
US4529456A (en) 1985-07-16
MY8700610A (en) 1987-12-31
FR2533751B1 (fr) 1988-11-10
IT8322983A0 (it) 1983-09-23
FR2533751A1 (fr) 1984-03-30
JPH0481337B2 (it) 1992-12-22
HK71087A (en) 1987-10-09

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970926