IT8521117A0 - Metodo di formazione di un isolante su di uno strato conduttivo configurato. - Google Patents

Metodo di formazione di un isolante su di uno strato conduttivo configurato.

Info

Publication number
IT8521117A0
IT8521117A0 IT8521117A IT2111785A IT8521117A0 IT 8521117 A0 IT8521117 A0 IT 8521117A0 IT 8521117 A IT8521117 A IT 8521117A IT 2111785 A IT2111785 A IT 2111785A IT 8521117 A0 IT8521117 A0 IT 8521117A0
Authority
IT
Italy
Prior art keywords
insulation
formation
conductive layer
configured conductive
layer
Prior art date
Application number
IT8521117A
Other languages
English (en)
Other versions
IT1190363B (it
Inventor
Russel Craig Ellwanger
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of IT8521117A0 publication Critical patent/IT8521117A0/it
Application granted granted Critical
Publication of IT1190363B publication Critical patent/IT1190363B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT21117/85A 1984-06-15 1985-06-12 Metodo di formazione di un isolante su di uno strato conduttivo configurato IT1190363B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/621,001 US4594769A (en) 1984-06-15 1984-06-15 Method of forming insulator of selectively varying thickness on patterned conductive layer

Publications (2)

Publication Number Publication Date
IT8521117A0 true IT8521117A0 (it) 1985-06-12
IT1190363B IT1190363B (it) 1988-02-16

Family

ID=24488323

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21117/85A IT1190363B (it) 1984-06-15 1985-06-12 Metodo di formazione di un isolante su di uno strato conduttivo configurato

Country Status (8)

Country Link
US (1) US4594769A (it)
JP (1) JPH0750702B2 (it)
CA (1) CA1229180A (it)
DE (1) DE3520083C2 (it)
FR (1) FR2566180B1 (it)
GB (1) GB2160359B (it)
IT (1) IT1190363B (it)
NL (1) NL8501688A (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4708767A (en) * 1984-10-05 1987-11-24 Signetics Corporation Method for providing a semiconductor device with planarized contacts
JPS62282446A (ja) * 1986-05-31 1987-12-08 Toshiba Corp 半導体装置の製造方法
NL8701717A (nl) * 1987-07-21 1989-02-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw.
US6074569A (en) * 1997-12-09 2000-06-13 Hughes Electronics Corporation Stripping method for photoresist used as mask in Ch4 /H2 based reactive ion etching (RIE) of compound semiconductors
US6319796B1 (en) 1999-08-18 2001-11-20 Vlsi Technology, Inc. Manufacture of an integrated circuit isolation structure
CN107665829B (zh) * 2017-08-24 2019-12-17 长江存储科技有限责任公司 晶圆混合键合中提高金属引线制程安全性的方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3962779A (en) * 1974-01-14 1976-06-15 Bell Telephone Laboratories, Incorporated Method for fabricating oxide isolated integrated circuits
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
US4044454A (en) * 1975-04-16 1977-08-30 Ibm Corporation Method for forming integrated circuit regions defined by recessed dielectric isolation
JPS5383467A (en) * 1976-11-30 1978-07-22 Nec Corp Production of semiconductor device
JPS53129970A (en) * 1977-04-20 1978-11-13 Hitachi Ltd Production of semiconductor device
US4222816A (en) * 1978-12-26 1980-09-16 International Business Machines Corporation Method for reducing parasitic capacitance in integrated circuit structures
EP0023146B1 (en) * 1979-07-23 1987-09-30 Fujitsu Limited Method of manufacturing a semiconductor device wherein first and second layers are formed
JPS5648140A (en) * 1979-09-27 1981-05-01 Seiko Epson Corp Manufacture of semiconductor device
JPS56108264A (en) * 1980-01-31 1981-08-27 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPS5750436A (en) * 1980-09-12 1982-03-24 Fujitsu Ltd Manufacture of semiconductor device
JPS58135645A (ja) * 1982-02-08 1983-08-12 Fujitsu Ltd 半導体装置の製造方法
US4481070A (en) * 1984-04-04 1984-11-06 Advanced Micro Devices, Inc. Double planarization process for multilayer metallization of integrated circuit structures

Also Published As

Publication number Publication date
FR2566180B1 (fr) 1989-07-28
GB2160359A (en) 1985-12-18
FR2566180A1 (fr) 1985-12-20
JPH0750702B2 (ja) 1995-05-31
IT1190363B (it) 1988-02-16
GB2160359B (en) 1988-02-24
GB8514823D0 (en) 1985-07-17
JPS6110257A (ja) 1986-01-17
DE3520083A1 (de) 1985-12-19
CA1229180A (en) 1987-11-10
US4594769A (en) 1986-06-17
DE3520083C2 (de) 1994-05-26
NL8501688A (nl) 1986-01-02

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970630