JPS5648140A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5648140A
JPS5648140A JP12449679A JP12449679A JPS5648140A JP S5648140 A JPS5648140 A JP S5648140A JP 12449679 A JP12449679 A JP 12449679A JP 12449679 A JP12449679 A JP 12449679A JP S5648140 A JPS5648140 A JP S5648140A
Authority
JP
Japan
Prior art keywords
psg
sio2
oxide film
high concentration
low concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12449679A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Hirakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP12449679A priority Critical patent/JPS5648140A/en
Publication of JPS5648140A publication Critical patent/JPS5648140A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate

Abstract

PURPOSE:To flatten an element surface without losing reliability by placing high concentration PSG on low concentration PSG, a CVD oxide film and a thermal oxide film. CONSTITUTION:SiO2 (Low concentration PSG) 301 is provided after diffusing a source and a drain and high concentration PSG 302 is placed on the SiO3 301. Then, the PSG 302 is flattened by reflowing. After that, with a plasma photo etching applied by using C2F5Cl gas, the SiO2 and PSG are etched at a uniform speed and the initial shape is maintained with a flat element shape. In this way, a flat element surface will be obtained by etching as far as a dashed line and a wafer warp and the expansion of a diffusion layer will not be generated.
JP12449679A 1979-09-27 1979-09-27 Manufacture of semiconductor device Pending JPS5648140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12449679A JPS5648140A (en) 1979-09-27 1979-09-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12449679A JPS5648140A (en) 1979-09-27 1979-09-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5648140A true JPS5648140A (en) 1981-05-01

Family

ID=14886925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12449679A Pending JPS5648140A (en) 1979-09-27 1979-09-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5648140A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594769A (en) * 1984-06-15 1986-06-17 Signetics Corporation Method of forming insulator of selectively varying thickness on patterned conductive layer
EP0368504A2 (en) * 1988-11-10 1990-05-16 Applied Materials, Inc. Method for planarizing an integrated circuit structure
US5077238A (en) * 1988-05-18 1991-12-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device with a planar interlayer insulating film
US5112776A (en) * 1988-11-10 1992-05-12 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing
US5173151A (en) * 1990-07-30 1992-12-22 Seiko Epson Corporation Method of dry etching in semiconductor device processing
US5204288A (en) * 1988-11-10 1993-04-20 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material
US5244841A (en) * 1988-11-10 1993-09-14 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594769A (en) * 1984-06-15 1986-06-17 Signetics Corporation Method of forming insulator of selectively varying thickness on patterned conductive layer
US5077238A (en) * 1988-05-18 1991-12-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device with a planar interlayer insulating film
EP0368504A2 (en) * 1988-11-10 1990-05-16 Applied Materials, Inc. Method for planarizing an integrated circuit structure
US5112776A (en) * 1988-11-10 1992-05-12 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing
US5204288A (en) * 1988-11-10 1993-04-20 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material
US5244841A (en) * 1988-11-10 1993-09-14 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing
US5173151A (en) * 1990-07-30 1992-12-22 Seiko Epson Corporation Method of dry etching in semiconductor device processing

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