JPS5565435A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5565435A
JPS5565435A JP13960978A JP13960978A JPS5565435A JP S5565435 A JPS5565435 A JP S5565435A JP 13960978 A JP13960978 A JP 13960978A JP 13960978 A JP13960978 A JP 13960978A JP S5565435 A JPS5565435 A JP S5565435A
Authority
JP
Japan
Prior art keywords
region
contacting
hole
etching
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13960978A
Other languages
Japanese (ja)
Inventor
Yutaka Torii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13960978A priority Critical patent/JPS5565435A/en
Publication of JPS5565435A publication Critical patent/JPS5565435A/en
Pending legal-status Critical Current

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  • Weting (AREA)

Abstract

PURPOSE: To provide a contacting hole having littlt side etching by attaching a lower layer film oxide to a semiconductor substrate and doping only the region, where a contacting hole is to be made, with impurities to speed up etching.
CONSTITUTION: The whole surface of semiconductor substrate 1, which is provided with a contact region 2, is covered with film oxide 3, whereupon a resistor 10 is provided, and here a window 10a for contacting smaller than the region 2 is punched out. Next, the part of the film 3 exposed within the window 10a is doped with the impurities having the concentration equal to, or more than the impurities concentration of PSG film 4 is attached to the whole surface. Thereafter upon this, a registing mask 10 having a window 5a, which is equally large as the former window 10a, is provided, and a contacting hole reaching down to the region 2 is opened by etching on the films 4 and 3. By doing so, etching speed is high on the hole region of the film 3 so that side etching is reduced and the hole is reduced to only in the contacting region.
COPYRIGHT: (C)1980,JPO&Japio
JP13960978A 1978-11-10 1978-11-10 Preparation of semiconductor device Pending JPS5565435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13960978A JPS5565435A (en) 1978-11-10 1978-11-10 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13960978A JPS5565435A (en) 1978-11-10 1978-11-10 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5565435A true JPS5565435A (en) 1980-05-16

Family

ID=15249261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13960978A Pending JPS5565435A (en) 1978-11-10 1978-11-10 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5565435A (en)

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