IT1271544B - Dispositivo di memoria con tempo di accesso ridotto delle celle di memoria in una modalita' di prova - Google Patents

Dispositivo di memoria con tempo di accesso ridotto delle celle di memoria in una modalita' di prova

Info

Publication number
IT1271544B
IT1271544B ITMI931153A ITMI931153A IT1271544B IT 1271544 B IT1271544 B IT 1271544B IT MI931153 A ITMI931153 A IT MI931153A IT MI931153 A ITMI931153 A IT MI931153A IT 1271544 B IT1271544 B IT 1271544B
Authority
IT
Italy
Prior art keywords
data
test mode
access time
memory device
memory
Prior art date
Application number
ITMI931153A
Other languages
English (en)
Inventor
Yuto Ikeda
Yoshinori Inoue
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI931153A0 publication Critical patent/ITMI931153A0/it
Publication of ITMI931153A1 publication Critical patent/ITMI931153A1/it
Application granted granted Critical
Publication of IT1271544B publication Critical patent/IT1271544B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

La presente invenzione si riferisce ad un dispositivo di memoria avente tempo di accesso ridotto delle celle di memoria in una modalità di prova. Questo dispositivo di memoria forma, nella modalità di prova, dati di lettura DR applicando elaborazioni EX-OR ad una pluralità di dati letti da una matrice a celle di memoria 11 tramite un circuito di elaborazione dei dati 5, per fornire all'esterno attraverso un circuito di uscita 6 i dati formati. La temporizzazione dell'uscita dei dati verso l'esterno viene ritardata, dal circuito di ritardo 12 nella modalità di prova, rispetto a quella nel funzionamento normale di un periodo di tempo corrispondente al tempo richiesto per l'elaborazione EX-OR nel circuito di elaborazione dei dati 5. Conseguentemente, può essere impedita l'uscita dei dati non validi verso l'esterno e quindi il tempo di accesso dei dati validi può essere ridotto.
ITMI931153A 1992-06-05 1993-06-01 Dispositivo di memoria con tempo di accesso ridotto delle celle di memoria in una modalita' di prova IT1271544B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4145749A JP3007475B2 (ja) 1992-06-05 1992-06-05 メモリ装置

Publications (3)

Publication Number Publication Date
ITMI931153A0 ITMI931153A0 (it) 1993-06-01
ITMI931153A1 ITMI931153A1 (it) 1994-12-01
IT1271544B true IT1271544B (it) 1997-05-30

Family

ID=15392269

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI931153A IT1271544B (it) 1992-06-05 1993-06-01 Dispositivo di memoria con tempo di accesso ridotto delle celle di memoria in una modalita' di prova

Country Status (5)

Country Link
US (1) US5361230A (it)
JP (1) JP3007475B2 (it)
KR (1) KR960010963B1 (it)
DE (1) DE4317926C2 (it)
IT (1) IT1271544B (it)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130654A (ja) * 1984-07-21 1986-02-12 Kanto Tokushu Seikou Kk アルミニウム連続鋳造用ロ−ルシエル鋼
US5455517A (en) * 1992-06-09 1995-10-03 International Business Machines Corporation Data output impedance control
JPH06275100A (ja) * 1993-03-19 1994-09-30 Fujitsu Ltd 半導体記憶装置
JPH06334513A (ja) * 1993-05-13 1994-12-02 Intel Corp データ処理装置
JP2806210B2 (ja) * 1993-06-15 1998-09-30 富士通株式会社 マイクロプロセッサ
JP2820016B2 (ja) * 1993-12-28 1998-11-05 日本電気株式会社 電子回路
US5579326A (en) * 1994-01-31 1996-11-26 Sgs-Thomson Microelectronics, Inc. Method and apparatus for programming signal timing
US5572535A (en) * 1994-07-05 1996-11-05 Motorola Inc. Method and data processing system for verifying the correct operation of a tri-state multiplexer in a circuit design
CA2200843C (en) * 1994-09-23 2006-01-17 Miriam Coller A marking composition
JPH0973775A (ja) * 1995-09-01 1997-03-18 Mitsubishi Electric Corp 半導体記憶装置
JP3607439B2 (ja) * 1996-11-11 2005-01-05 株式会社日立製作所 半導体集積回路装置
KR100222970B1 (ko) * 1997-01-29 1999-10-01 윤종용 전자장치의 테스트모드 수행방법
US6418547B1 (en) * 1998-02-26 2002-07-09 Micron Technology, Inc. Internal guardband for semiconductor testing
KR20020031874A (ko) * 2000-10-24 2002-05-03 이철수 비밀잉크 조성물 및 그 발색 조성물
KR20020065961A (ko) * 2001-02-08 2002-08-14 이철수 위조 및 변조 불가 보안용지 및 그 발색도포구
US6675273B2 (en) 2001-05-31 2004-01-06 International Business Machines Corporation Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requested
DE10143455B4 (de) * 2001-09-05 2005-12-15 Infineon Technologies Ag Verfahren und Vorrichtung zum Testen von zu testenden Schaltungseinheiten mit erhöhter Datenkompression für Burn-in
FR2854967B1 (fr) * 2003-05-13 2005-08-05 St Microelectronics Sa Procede et dispositif d'identification d'un mode de fonctionnement d'un dispositif controle, par exemple un mode test d'une memoire eeprom
KR100583152B1 (ko) * 2004-02-19 2006-05-23 주식회사 하이닉스반도체 데이터 억세스타임 측정모드를 갖는 반도체 메모리 소자
CN104932961B (zh) * 2015-05-28 2019-01-11 广东小天才科技有限公司 检测终端设备中数据线邦定断路的方法和装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4608669A (en) * 1984-05-18 1986-08-26 International Business Machines Corporation Self contained array timing
JPS61289449A (ja) * 1985-06-18 1986-12-19 Nec Corp 高速メモリ診断処理装置
US4630239A (en) * 1985-07-01 1986-12-16 Motorola, Inc. Chip select speed-up circuit for a memory
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
JPH03250348A (ja) * 1990-02-28 1991-11-08 Nec Corp メモリの診断方式

Also Published As

Publication number Publication date
US5361230A (en) 1994-11-01
KR960010963B1 (ko) 1996-08-14
ITMI931153A1 (it) 1994-12-01
KR940006148A (ko) 1994-03-23
JP3007475B2 (ja) 2000-02-07
JPH05342114A (ja) 1993-12-24
ITMI931153A0 (it) 1993-06-01
DE4317926C2 (de) 1996-04-04
DE4317926A1 (de) 1993-12-09

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970725